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Welcome to Discourse
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0
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525
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January 7, 2020
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Using DPI-C (via SV Wrapper) to work with UVVM
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0
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43
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March 14, 2024
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How to send Avalon-ST packages with increasing channel signal within that package?
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0
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38
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March 6, 2024
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Verification components for GRLIB
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0
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44
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March 5, 2024
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VVC generated file version-information request
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2
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540
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February 29, 2024
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I2C VVC Variable Data Length
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0
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67
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February 27, 2024
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Compilation error in the VVC commond methods after setting t_vvc_result as record
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1
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46
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February 20, 2024
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UVVM compilation warning using VUNIT
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2
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81
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February 15, 2024
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Questasim script error during compilation after a syntax error
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0
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64
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February 14, 2024
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SPI BFM error run time in sample code
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3
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135
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February 11, 2024
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SPI BFM spi_slave_transmit exit time
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6
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266
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January 21, 2024
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Scoreboard with multiple expected queues
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1
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124
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December 28, 2023
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Issues with generated files
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0
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78
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December 13, 2023
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Symbol __mcode_rem_ov_i64 is undefined
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0
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92
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December 12, 2023
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Uart_monitor procedure
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1
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146
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October 18, 2023
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Issue on bitvis_vip_scoreboard
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2
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123
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October 18, 2023
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Simulation stopped when transmitting with axistream_transmit() VVC
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9
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250
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October 18, 2023
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Collisions with Tready in Axi-Stream UVVM
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3
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127
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October 11, 2023
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Library utils with "context" in Modelsim with UVVM-Master
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4
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134
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October 18, 2023
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Is there any possible method to print recieve data frame after rgmii_expect() in RGMII VVC?
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3
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252
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September 16, 2023
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UVVM Verification Tests Reporting Errors as "Passed" in Questa Verification Run Manager
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0
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151
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August 31, 2023
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VIP GPIO expect on a bus
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2
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176
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August 22, 2023
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How to exceed queue limit of 1000 elements?
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3
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232
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August 16, 2023
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Problem with axilite writing by using VVC
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3
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149
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August 16, 2023
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Axistream_receive does not work
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9
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220
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August 10, 2023
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UVVM support GHDL open source simulator
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9
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1053
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August 4, 2023
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Sbi_read and fetch_result return length
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5
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259
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July 12, 2023
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Simulating with vhdl and verilog
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1
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216
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May 31, 2023
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VIP wrapper or new custom VIP
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1
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185
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May 22, 2023
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HDLRegression - test suite regression tool
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1
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288
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October 19, 2022
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