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About the General questions category
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0
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388
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May 6, 2021
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Suggestion for an engaged community
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1
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13
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August 22, 2024
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Verification for simple parallel bus with data valid
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2
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55
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August 1, 2024
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Wait_on_bfm_sync_start()... why?
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1
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30
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July 11, 2024
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UVVM vs OSVVM: The main benefits – and some history
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2
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574
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June 21, 2024
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ALDEC Active-HDL supported?
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9
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1014
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June 10, 2024
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Active-hdl VVC usage
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0
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41
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May 28, 2024
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AXI Verification Components, OSVVM vs UVVM
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0
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56
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May 10, 2024
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Using DPI-C (via SV Wrapper) to work with UVVM
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0
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76
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March 14, 2024
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Questasim script error during compilation after a syntax error
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0
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128
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February 14, 2024
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UVVM Verification Tests Reporting Errors as "Passed" in Questa Verification Run Manager
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0
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190
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August 31, 2023
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UVVM support GHDL open source simulator
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9
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1206
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August 4, 2023
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Simulating with vhdl and verilog
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1
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278
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May 31, 2023
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VIP wrapper or new custom VIP
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1
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234
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May 22, 2023
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UVVM in Vivado / xsim
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4
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438
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April 21, 2023
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Driving UVVM simulations using GNU make
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11
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656
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January 17, 2023
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VVM for teaching verification at a UK university
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1
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334
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October 31, 2022
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No feasible entries error
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3
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370
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August 5, 2022
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Using two clocks with different phases
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1
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294
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August 3, 2022
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" Failed to acquire semaphore when sending command to VVC"
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4
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520
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July 8, 2022
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UVVM and MicroBlaze simulation
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1
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357
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May 23, 2022
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Documentation: Can you use normal qoute marks in example code in the documentation?
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1
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375
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December 16, 2021
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Questa Compilation Error for Ethernet Testbench
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1
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386
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November 8, 2021
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Disable all logging, only report when an error or failure occurs
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2
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457
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October 29, 2021
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We have published beginner guides for UVVM and UVVM Light
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0
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628
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May 12, 2020
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Test bench hangs up on wait statement
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5
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573
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February 2, 2021
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Is it possible to let two VVC's talk to each other?
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2
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472
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November 11, 2020
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Could older releases in zipformat be also made available trough the forum?
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1
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466
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September 11, 2020
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Can you have multiple UVVM releases side by side
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2
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443
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August 18, 2020
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Best practices when combining assertion based testing with UVVM
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3
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840
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September 2, 2023
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