Library utils with "context" in Modelsim with UVVM-Master

Utility Library
1

Hello!

I am having problems using UVVM-master in Modelsim, I have a project that I know it works in vivado and I wanted to try simulating it with UVVM-Master in Modelsim.

the version of Modelsim DE-64 is 10.7 and the UVVM-master is the last one.

The issue is that when using the UVVM-Utils libraries we have to use the “context” type variable and modelsim shows me a “syntax error” near context. I attach evidence.

Context Error
Context Error874×663 92.6 KB

Libraries used:
–TYPICAL LIBRARIES
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.math_real.all;

– UVVM UTIL LIBRARIES
library uvvm_util;
context uvvm_util.uvvm_util_context; – Here is the error (near context)

– UVVM VVC FRAMEWORK LIBRARIES
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;

– AXISTREAM LIBRARIES
library bitvis_vip_axistream;
use bitvis_vip_axistream.axistream_bfm_pkg.all;

– FILE READING/WRITING LIBRARIES
library STD;
use std.env.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use std.env.finish;

This project uses the following versions:
uvvm_util, version v2.19.2
uvvm_vvc_framework, version v2.12.4
bitvis_irqc, version v1.0.12
bitvis_uart, version v1.1.6
bitvis_vip_avalon_mm, version v2.8.4
bitvis_vip_avalon_st, version v1.2.4
bitvis_vip_axilite, version v2.9.3
bitvis_vip_axistream, version v4.7.7
bitvis_vip_clock_generator, version v1.5.2
bitvis_vip_error_injection, version v1.0.0
bitvis_vip_gmii, version v1.0.1
bitvis_vip_gpio, version v1.8.5
bitvis_vip_i2c, version v2.7.3
bitvis_vip_rgmii, version v1.0.1
bitvis_vip_sbi, version v2.8.3
bitvis_vip_scoreboard, version v2.3.1
bitvis_vip_spi, version v3.9.5
bitvis_vip_uart, version v2.8.6
bitvis_vip_spec_cov, version v1.0.0
bitvis_vip_hvvc_to_vvc_bridge, version v0.1.1
bitvis_vip_ethernet, version v0.2.2
bitvis_vip_axi, version v1.0.1
bitvis_vip_wishbone, version v0.1.2 BETA

I followed the steps of this URL: A UVVM EXAMPLE UART TRANSMITTER TESTBENCH SIMULATION on MODELSIM – Mehmet Burak Aykenar
The difference is that I have used UVVM-Master in spite of UVVM-light.
I have tried with the UVVM-master version of 2017, the same year as my Modelsim, but with the same error.

1 Like
2

Hi.
This seem to be a simulator bug. If it is a show stopper for you, you can switch that line with the files listed inside the uvvm_util_context.vhd file.

Best regards,
Marius

3

Hi,

I think you are compiling with VHDL 2002, you need to compile with 2008 for context to work.

4

Hello!

It worked!
Thank you so much!