Problem with axilite writing by using VVC

Hi everyone.
I’m trying to make a simple testbench for AXI Lite but the following error appears: timeout for uvvm cmd, while waiting for acknowledge vvc, I read in this forum that it could be solved by increasing the completition time with await_completition() function but it hasn’t worked for me, I appreciate your help.
My code is the following:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_axilite;
context bitvis_vip_axilite.vvc_context;

entity axilitevvc_indra_tb is
end;

architecture bench of axilitevvc_indra_tb is

component axilitevvc_indra
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component;

constant C_S_AXI_DATA_WIDTH : integer := 32;
constant C_S_AXI_ADDR_WIDTH : integer := 4;
constant C_CLK_PERIOD : time:= 10 ns;
signal clock_ena : boolean := true;
signal S_AXI_ACLK : std_logic;
signal S_AXI_ARESETN : std_logic;
signal S_AXI_AWADDR : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal S_AXI_AWPROT : std_logic_vector(2 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal S_AXI_WSTRB : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal S_AXI_ARPROT : std_logic_vector(2 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic ;
signal axilite_if: t_axilite_if
(
write_address_channel(
awaddr(C_S_AXI_ADDR_WIDTH-1 downto 0)
),
write_data_channel(
wdata(C_S_AXI_DATA_WIDTH-1 downto 0),
wstrb(4-1 downto 0)
),
read_address_channel(
araddr(C_S_AXI_ADDR_WIDTH-1 downto 0)
),
read_data_channel(
rdata(C_S_AXI_DATA_WIDTH-1 downto 0)
)
);
begin

uut: axilitevvc_indra generic map ( C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH )
port map ( S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => axilite_if.write_address_channel.awaddr,
S_AXI_AWPROT => axilite_if.write_address_channel.awprot,
S_AXI_AWVALID => axilite_if.write_address_channel.awvalid,
S_AXI_AWREADY => axilite_if.write_address_channel.awready,
S_AXI_WDATA => axilite_if.write_data_channel.wdata,
S_AXI_WSTRB => axilite_if.write_data_channel.wstrb,
S_AXI_WVALID => axilite_if.write_data_channel.wvalid,
S_AXI_WREADY => axilite_if.write_data_channel.wready,
S_AXI_BRESP => axilite_if.write_response_channel.bresp,
S_AXI_BVALID => axilite_if.write_response_channel.bvalid,
S_AXI_BREADY => axilite_if.write_response_channel.bready,
S_AXI_ARADDR => axilite_if.read_address_channel.araddr,
S_AXI_ARPROT => axilite_if.write_address_channel.awprot,
S_AXI_ARVALID => axilite_if.read_address_channel.arvalid,
S_AXI_ARREADY => axilite_if.read_address_channel.arready,
S_AXI_RDATA => axilite_if.read_data_channel.rdata,
S_AXI_RRESP => axilite_if.read_data_channel.rresp,
S_AXI_RVALID => axilite_if.read_data_channel.rvalid,
S_AXI_RREADY => axilite_if.read_data_channel.rready );

i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
clock_generator(S_AXI_ACLK, clock_ena, C_CLK_PERIOD, “AXI Lite Clock Signal”);
gen_pulse(S_AXI_ARESETN,‘0’, 2*C_CLK_PERIOD, “AXI Lite Reset Signal”);

p_axiliteVVC:
process

begin

axilite_if <= init_axilite_if_signals(C_S_AXI_ADDR_WIDTH,C_S_AXI_DATA_WIDTH);
shared_axilite_vvc_config(1).bfm_config.clock_period := C_CLK_PERIOD;

wait_until_given_time_after_rising_edge(S_AXI_ACLK,3*C_CLK_PERIOD);

log("WRITING BY USING VCC FOR AXILITE");

axilite_write(AXILITE_VVCT, 1, x"F", x"00000054", "Written data");

await_completion(AXILITE_VVCT, 1, 1000 ns);

wait;

end process;

end;

Hi,
Where do instantiate the VVC?

Br
Marius

Hi Marius.
I didn’t know that I’ve got to do so, can you give an example of it ?
The only thing that I’ve instantiated is the following:
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
I’m not completely sure if I’m using the whole set of needed libraries for axilite VVC.

The VVC is an entity, so you need to instantiate it as you would with any other entity.
That would be something like this:

  axilite_vvc : entity bitvis_vip_axilite.axilite_vvc
    generic map(
      GC_ADDR_WIDTH   => C_ADDR_WIDTH,
      GC_DATA_WIDTH   => C_DATA_WIDTH,
      GC_INSTANCE_IDX => C_AXILITE_VVC_IDX
    )
    port map(
      clk                   => clk,
      axilite_vvc_master_if => axilite_if
    );

where C_AXILITE_VVC_IDX is a constant for the instance number for your VVC, e.g. 1. And you use the same number/constant when calling the VVC methods and other methods that interacts with the VVC - such as await_completion(). C_ADDR_WIDTH and C_DATA_WIDTH are other constants that you need to define. You can have a look at the documentation for this in the VVC QR - page 2.

Your code will then use this number/constant:

axilite_write(AXILITE_VVCT, C_AXILITE_VVC_IDX, x"F", x"00000054", "Written data");
await_completion(AXILITE_VVCT, C_AXILITE_VVC_IDX, 1000 ns);

Br,
Marius

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