Hi, I’ve been trying to somehow simulate a project including vhdl and verilog files. Is it possible ? I’ve read that people done it using yosys with ghdl-plugin in it but the whole explanation how they done it, was a bit confusing to me and that didnt got me far.
This depends on the simulator you are using. I belive that GHDL does not have Verilog support, but there may be solutions such as using the yosys-ghdl-plugin.