I am verifying a DMA engine which has multiple AXI stream slave interfaces and a single AXI stream master interface. I have managed to generate a basic testbench using UVVM light and axistream BFMs and am now trying to create a more comprehensive testbench using VVCs.
I understand from the documentation that a slave VVC should only have a single scoreboard associated with it. I envisage some logic to look at the TID (which defines which slave interface the data is associated with) and a mechanism to check this data against the the corresponding expected queue. Hence the scoreboard would need to support multiple expected queues.
- Any obvious issues with this approach or suggestions on a better way to proceed?
- I notice that the axistream VVC does not currently feature a scoreboard - are there any examples of how this might be done as this seems to be the logical place to incorporate this functionality?