I’ve been coding a testbench for axistream with UVVM Light, my design file was done by using the AXI stream slave generated with Vivado, so I’m just making the testbench using UVVM. I can write data with axistream_write() but when using axistream_read() an overload error appears. If anyone can help me would be greate, the testbench that I’ve doing is shown below:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library STD;
use std.env.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use std.env.finish;
use uvvm_util.axistream_bfm_pkg.all;
entity AxistreamBlock_v1_0_S00_AXIS_tb is
end;
architecture bench of AxistreamBlock_v1_0_S00_AXIS_tb is
component AxistreamBlock_v1_0_S00_AXIS
generic (
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port (
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN: in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic
);
end component;
constant C_S_AXIS_TDATA_WIDTH :integer:=32;
constant C_S_AXIS_TUSER_WIDTH :integer:=1;
constant C_S_AXIS_TVALID_WIDTH :integer:=1;
constant C_S_AXIS_TLAST_WIDTH :integer:=1;
constant C_S_AXIS_TREADY_WIDTH :integer:=1;
constant C_S_AXIS_TID_WIDTH :integer:=1;
constant C_S_AXIS_TDEST_WIDTH :integer:=1;
constant C_CLK_PERIOD : time:= 10 ns;
signal clock_ena : boolean := true;
signal S_AXIS_ACLK : std_logic;
signal S_AXIS_ARESETN : std_logic;
signal S_AXIS_TREADY : std_logic;
signal S_AXIS_TDATA : std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
signal S_AXIS_TSTRB : std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
signal S_AXIS_TLAST : std_logic;
signal S_AXIS_TVALID : std_logic ;
signal axistream_if : t_axistream_if
(
tdata (C_S_AXIS_TDATA_WIDTH-1 downto 0), – Data. Width is constrained when the procedure is called
tkeep ((C_S_AXIS_TDATA_WIDTH / 8) - 1 downto 0), – One valid-bit per data byte
tuser (C_S_AXIS_TUSER_WIDTH-1 downto 0), – User sideband data
tstrb ((C_S_AXIS_TDATA_WIDTH / 8) - 1 downto 0), – Treated as sideband data by BFM: tstrb does not affect tdata
tid (C_S_AXIS_TID_WIDTH-1 downto 0), – Treated as sideband data by BFM
tdest (C_S_AXIS_TDEST_WIDTH-1 downto 0) – Treated as sideband data by BFM
)
;
signal axistream_bfm_config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
– Overloaded version without records
procedure axistream_receive(
variable data_array : inout t_slv_array;
variable data_length : inout natural; – Number of bytes received
variable strb_array : inout t_strb_array;
constant msg : in string;
signal clk : in std_logic
)is
begin
-- Call the record version
axistream_receive(
data_array => data_array,
data_length => data_length,
strb_array => strb_array,
msg => msg,
clk => clk);
end procedure axistream_receive;
begin
– Insert values for generic parameters !!
uut: AxistreamBlock_v1_0_S00_AXIS generic map ( C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH )
port map (
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TREADY => S_AXIS_TREADY,
–S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TDATA => axistream_if.tdata,
–S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TSTRB =>axistream_if.tstrb,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => axistream_if.tvalid
–S_AXIS_TVALID => S_AXIS_TVALID
);
clock_generator(S_AXIS_ACLK, clock_ena, C_CLK_PERIOD, “Reloj del AXI Stream”);
gen_pulse(S_AXIS_ARESETN,‘0’, 2*C_CLK_PERIOD, “Pulsed reset-signal - active for 1 T”);
p_sequencer_axistr: process is
variable v_dato : std_logic_vector(C_S_AXIS_TDATA_WIDTH- 1 downto 0);
begin
axistream_if <= init_axistream_if_signals(true, axistream_if.tdata'length, axistream_if.tuser'length, axistream_if.tid'length, axistream_if.tdest'length);
wait_until_given_time_after_rising_edge(S_AXIS_ACLK,C_CLK_PERIOD);
axistream_bfm_config.clock_period <= C_CLK_PERIOD;
log("INICIO DE ESCRITURA");
S_AXIS_TVALID<='1';
wait_until_given_time_after_rising_edge(S_AXIS_ACLK,2*C_CLK_PERIOD);
axistream_transmit(x"0F0A0C02","Sent Bytes",S_AXIS_ACLK,axistream_if);
wait_until_given_time_after_rising_edge(S_AXIS_ACLK,2*C_CLK_PERIOD);
v_dato:=x"0F0A0C02";
axistream_receive(v_dato,"Bytes Recibidos",S_AXIS_ACLK,axistream_if);
wait_until_given_time_after_rising_edge(S_AXIS_ACLK,C_CLK_PERIOD);
wait;
end process;
end;
