Verification for simple parallel bus with data valid

General questions
1

Hello,
I’m using UVVM to verify a DUT that has a simple data output bus which consists of 16 parallel bits and a data valid bit. What is the right UVVM module I can use to queue up checks for the expected values coming out of my DUT?

Thanks

2

Hi,
Currently your best choice would be to use AXI-stream or Avalon-stream.
Note however, that the signal records for these protocols in UVVM contain the complete set of protocol signals. You thus need to connect up ‘data’ and ‘valid’ and set the rest to “passive” values (i.e. set record element ‘tready’ fixed to ‘1’ in your TB).
I guess we could evaluate making a simpler BFM and VVC for this purpose, but that is not top priority just now. Do you only have single word accesses?

3

Yes. I just need to read one word at a time. I ended up making my own simple interface using the GPIO BFM and a bunch of procedure calls. I didn’t feel like making my own VVC.

4

Good to hear you found a solution.
Note that you can use the vvc_generator.py script to develop your own VVC and BFM.