No feasible entries error


Apologies in advance if this is too naive or basic question since I am learning UVVM and encountering problems and Google is unable to help.

I am setting an enable signal in the TB using gpio_bfm_pkg using following command (tried both)

gpio_set(en,"Setting enable to 1",1);
gpio_set(en,"Setting enable to 1",'1');

where en is defined as std_logic but I get error complaining

(vcom-1600) No feasible entries for subprogram “gpio_set”.

I think this corresponds to that I am not using the command in correct way but apparently I don’t see any problem. Maybe gpio_set expects vector but I dont want to give it a vector input even though it is a single bit. Anyone has some better suggestions?


gpio_set() is only defined for std_logic_vector and not for std_logic.
UVVM/gpio_bfm_pkg.vhd at master · UVVM/UVVM · GitHub line 62.
There is no overload for std_logic, so you need to convert/cast/change to std_logic_vector.

– Espen

Thank you Espen for the reply,

Actually I thought the same workaround but I didn’t think it’d be a good workaround as it might cause some unknown problems since the signal was used at multiple places in different ways.

And since it is someone else’s code, I would not like to change its structure by typecasting multiple logical signals in the code.

Is it possible to create my own bfm that supports std_logic? Is there any ref doc for that?


You can create your own BFM, but it would be much easier to just create a wrapper procedure that takes a std_logic and converts it to std_logic_vector and calls the gpio_set/get() BFM procedure inside your testbench .


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