" Failed to acquire semaphore when sending command to VVC"

Hello, I am trying to do a simple verification of an SPI module using a SPI VVC and SBI VVC. I don’t have a lot of experience with uvvm but I think I have set it up correctly but any invocation of VVC command, e.g.

sbi_write(SBI_VVCT, 1, x"1000", x"40", "Set baud rate to 9600");

results in the message: " Failed to acquire semaphore when sending command to VVC".
I don’t know what this means.

I will note that I am using Modelsim version 10.4 which is older so maybe that’s a reason.

I hope someone can point me in the right direction. thanks.

Here is the log output:

Time: 0 ps Iteration: 0 Region: /methods_pkg File: C:/Users/mike/Documents/BTI_Projects/DSP_FIR_IIR_sandbox/FlatHierarchy/src/uvvm/script/…/uvvm_util/script/…/src/methods_pkg.vhd

Loading uvvm_util.bfm_common_pkg(body)

Loading uvvm_util.generic_queue_pkg(body)

Loading uvvm_util.rand_pkg(body)

Loading uvvm_util.func_cov_pkg(body)

Loading uvvm_vvc_framework.ti_protected_types_pkg(body)

Loading uvvm_vvc_framework.ti_vvc_framework_support_pkg(body)

Loading bitvis_vip_clock_generator.vvc_cmd_pkg(body)

Loading bitvis_vip_clock_generator.td_target_support_pkg(body)

Loading bitvis_vip_clock_generator.vvc_methods_pkg(body)

Loading bitvis_vip_clock_generator.td_vvc_framework_common_methods_pkg(body)

Loading bitvis_vip_spi.transaction_pkg

Loading bitvis_vip_scoreboard.generic_sb_support_pkg(body)

Loading bitvis_vip_spi.spi_bfm_pkg(body)

Loading bitvis_vip_spi.vvc_cmd_pkg(body)

Loading bitvis_vip_spi.td_target_support_pkg(body)

Loading bitvis_vip_spi.td_vvc_framework_common_methods_pkg(body)

Loading bitvis_vip_scoreboard.generic_sb_pkg(body)

Loading bitvis_vip_spi.vvc_methods_pkg(body)

Loading bitvis_vip_sbi.transaction_pkg

Loading bitvis_vip_sbi.sbi_bfm_pkg(body)

Loading bitvis_vip_sbi.vvc_cmd_pkg(body)

Loading bitvis_vip_sbi.td_target_support_pkg(body)

Loading bitvis_vip_sbi.vvc_methods_pkg(body)

Loading bitvis_vip_sbi.td_vvc_framework_common_methods_pkg(body)

Loading misc_function.misc_function(body)

Loading bitvis_vip_spi.td_cmd_queue_pkg

Loading bitvis_vip_spi.td_result_queue_pkg

Loading bitvis_vip_spi.td_vvc_entity_support_pkg(body)

Loading bitvis_vip_sbi.td_cmd_queue_pkg

Loading bitvis_vip_sbi.td_result_queue_pkg

Loading bitvis_vip_sbi.td_vvc_entity_support_pkg(body)

Loading ieee.std_logic_arith(body)

Loading ieee.std_logic_unsigned(body)

Loading bitvis_vip_clock_generator.td_cmd_queue_pkg

Loading bitvis_vip_clock_generator.td_result_queue_pkg

Loading bitvis_vip_clock_generator.td_vvc_entity_support_pkg(body)

Loading sim_lib.testbench_spi_module(sim)

Loading uvvm_vvc_framework.ti_uvvm_engine(func)

Loading bitvis_vip_spi.spi_vvc(behave)

Loading bitvis_vip_sbi.sbi_vvc(behave)

Loading spi_module_lib.spi_module(behavioral)

Loading bitvis_vip_clock_generator.clock_generator_vvc(behave)

UVVM: ID_CONSTRUCTOR 0.0 ns CLOCK_GENERATOR_VVC,1 VVC instantiated.

UVVM: ID_CONSTRUCTOR_SUB 0.0 ns CLOCK_GENERATOR_VVC,1 Command queue instantiated and will give a warning when reaching 1000 elements in queue.

UVVM: ID_CONSTRUCTOR_SUB 0.0 ns CLOCK_GENERATOR_VVC,1 Result queue instantiated and will give a warning when reaching 1000 elements in queue.

UVVM: ID_CONSTRUCTOR 0.0 ns SBI_VVC,1 VVC instantiated.

UVVM: ID_CONSTRUCTOR_SUB 0.0 ns SBI_VVC,1 Command queue instantiated and will give a warning when reaching 1000 elements in queue.

UVVM: ID_CONSTRUCTOR_SUB 0.0 ns SBI_VVC,1 Result queue instantiated and will give a warning when reaching 1000 elements in queue.

UVVM: ID_CONSTRUCTOR 0.0 ns SPI_VVC,1 VVC instantiated.

UVVM: ID_CONSTRUCTOR_SUB 0.0 ns SPI_VVC,1 Command queue instantiated and will give a warning when reaching 1000 elements in queue.

UVVM: ID_CONSTRUCTOR_SUB 0.0 ns SPI_VVC,1 Result queue instantiated and will give a warning when reaching 1000 elements in queue.

UVVM: ID_UVVM_SEND_CMD 0.0 ns TB seq.(uvvm) ->start_clock(CLOCK_GENERATOR_VVC,1): ‘Starting clock’. [1]

UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns CLOCK_GENERATOR_VVC,1 …Interpreter: Waiting for command

UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns SBI_VVC,1 …Interpreter: Waiting for command

UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns SPI_VVC,1 …Interpreter: Waiting for command

UVVM: ID_CTRL 0.0 ns SBI_VVC_SB,1 enable() => SB enabled. ‘SBI VVC SB Enabled’

UVVM: ID_CTRL 0.0 ns SBI_VVC_SB,1 config() => config applied to SB.

UVVM: ID_CTRL 0.0 ns SBI_VVC_SB,1 enable_log_msg() => message id id_data enabled.

UVVM: ID_CTRL 0.0 ns SPI_VVC_SB,1 enable() => SB enabled. ‘SPI VVC SB Enabled’

UVVM: ID_CTRL 0.0 ns SPI_VVC_SB,1 config() => config applied to SB.

UVVM: ID_CTRL 0.0 ns SPI_VVC_SB,1 enable_log_msg() => message id id_data enabled.

UVVM: ID_CMD_INTERPRETER 0.0 ns CLOCK_GENERATOR_VVC,1 start_clock(CLOCK_GENERATOR_VVC,1). Command received [1]

UVVM: ID_CMD_EXECUTOR 0.0 ns CLOCK_GENERATOR_VVC,1 start_clock(CLOCK_GENERATOR_VVC,1) - Will be executed [1]

UVVM:

UVVM:

UVVM: ID_LOG_HDR 0.0 ns TB seq. Configuring VVCs

UVVM: ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

UVVM:

UVVM:

UVVM: ID_LOG_HDR 0.0 ns TB seq. SPI Module- Testbench

UVVM: ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

UVVM: ID_SEQUENCER 0.0 ns TB seq.

UVVM:

UVVM:

UVVM: ID_LOG_HDR 0.0 ns TB seq. do stuff…

UVVM: ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

UVVM: ID_UVVM_CMD_ACK 0.0 ns TB seq.(uvvm) ACK received. [1]

UVVM: ID_CLOCK_GEN 0.0 ns CLOCK_GENERATOR_VVC,1 Clock ‘clk’ started

UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns SBI_VVC,1 …Executor: Waiting for command

UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns SPI_VVC,1 …Executor: Waiting for command

UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns CLOCK_GENERATOR_VVC,1 …Interpreter: Waiting for command

UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns CLOCK_GENERATOR_VVC,1 …Executor: Waiting for command

UVVM:

UVVM: =============================================================================================================================================================================================

UVVM: *** TB_ERROR #1 ***

UVVM: 100 ns TB seq.(uvvm)

UVVM: Failed to acquire semaphore when sending command to VVC

UVVM:

UVVM: Simulator has been paused as requested after 1 TB_ERROR

UVVM: *** To find the root cause of this alert, step out the HDL calling stack in your simulator. ***

UVVM: *** For example, step out until you reach the call from the test sequencer. ***

UVVM: =============================================================================================================================================================================================

UVVM:

UVVM:

** Note: stop

Time: 100 ns Iteration: 500 Instance: /testbench_spi_module

Break in Subprogram alert at C:/Users/mike/Documents/BTI_Projects/DSP_FIR_IIR_sandbox/FlatHierarchy/src/uvvm/script/…/uvvm_util/script/…/src/methods_pkg.vhd line 3702

Stopped at C:/Users/mike/Documents/BTI_Projects/DSP_FIR_IIR_sandbox/FlatHierarchy/src/uvvm/script/…/uvvm_util/script/…/src/methods_pkg.vhd line 3702

Hi,
Did you initialize the UVVM environment in your testbench or test-harness? I.e. include this entity

i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;

You will also need to stall your testbench sequencer to allow for the UVVM framework to be ready

await_uvvm_initialization(VOID)

See uvvm_vvc_framework/doc/UVVM_VVC_Framework_Essential_Mechanisms.pdf

Br,
Marius

Hi, thanks but I am doing that in the testbench.

I am suspecting the old simulator Modelsim 10.6 might be a problem here as the testbench is very simple.

I posting the code here in case I did something wrong:

library misc_function;
library spi_module_lib;
library uvvm_util;
library bitvis_vip_spi;
library bitvis_vip_sbi;
library uvvm_vvc_framework;
library bitvis_vip_clock_generator;

context uvvm_util.uvvm_util_context;
context bitvis_vip_clock_generator.vvc_context;
context bitvis_vip_spi.vvc_context;
context bitvis_vip_sbi.vvc_context;

use bitvis_vip_sbi.sbi_bfm_pkg.init_sbi_if_signals;
use misc_function.misc_function.all;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;

ENTITY testbench_spi_module IS
END testbench_spi_module;

ARCHITECTURE sim OF testbench_spi_module IS

constant clk_period : time := 20 ns;

--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';

signal	spi_data_in_i : STD_LOGIC_VECTOR(7 downto 0);
signal	spi_data_out_i : STD_LOGIC_VECTOR(7 downto 0);
signal	spi_write_req_i : STD_LOGIC;
signal	spi_busy_i : STD_LOGIC;
		
signal	spi_CPOL_i : STD_LOGIC;   
signal 	spi_CPHA_i : STD_LOGIC;  
signal	spi_MISO_i : STD_LOGIC;
signal  SPI_CLK : STD_LOGIC;
signal  SPI_MISO : STD_LOGIC;
signal  SPI_MOSI : STD_LOGIC;
signal  SPI_CS: STD_LOGIC;

signal SPI_BUS : t_spi_if;
signal SBI_BUS : t_sbi_if (addr(7 downto 0), -- Seems you have to define the length for subtypes with variable lengths otherwise it will complain about undefined
   				 wdata(7 downto 0),
    			rdata(7 downto 0))	:= init_sbi_if_signals(8, 8);


-- Configuration of the SPI bus timings
constant SPI_BFM_CONFIG: t_spi_bfm_config := (
	CPOL             => '0',
	CPHA             => '0',
	spi_bit_time     => 10000 ns,  -- Make sure we notice if we forget to set bit time.
	ss_n_to_sclk     => 20 ns,
	sclk_to_ss_n     => 20 ns,
	inter_word_delay => 0 ns,
	match_strictness => MATCH_EXACT,
	id_for_bfm       => ID_BFM,
	id_for_bfm_wait  => ID_BFM_WAIT,
	id_for_bfm_poll  => ID_BFM_POLL
);

BEGIN

 -- Every UVVM testbench using VVCs must instantiate the UVVM engine module
UVVM_ENGINE : entity uvvm_vvc_framework.ti_uvvm_engine(func);

-- Instantiate  instance 1 of SPI VVC
i1_spi_vvc: entity bitvis_vip_spi.spi_vvc
generic map(
	GC_INSTANCE_IDX   => 1,
	GC_MASTER_MODE => false
)
port map(
	spi_vvc_if => SPI_BUS
);


SPI_BUS.ss_n <= SPI_CS;
SPI_BUS.sclk <= SPI_clk;
SPI_BUS.mosi <= SPI_MOSI;
SPI_BUS.miso <= SPI_MISO;


-- Instantiate instance one of SBI VVC
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
	GC_INSTANCE_IDX	=> 1,
	GC_ADDR_WIDTH	=> 8,
	GC_DATA_WIDTH	=> 8
)
port map(
	clk => clk,
	sbi_vvc_master_if => SBI_BUS
);
			       
			       

SBI_BUS.cs <= spi_write_req_i ;
SBI_BUS.addr(7 downto 0) <= (others => '0');
SBI_BUS.wena <= '0';
SBI_BUS.rena <= '0';
SBI_BUS.wdata(7 downto 0) <= spi_data_in_i;
SBI_BUS.ready <= '0';
SBI_BUS.rdata(7 downto 0) <=spi_data_out_i;


-- DUT
DUT : entity spi_module_lib.spi_module
generic map (
    	SPI_HALF_CYCLE => 10,  -- 25 cycle (50 cycle for SPI period)
    	SPI_CPOL_MODE => '0',               -- clock polarity (1 = high)
    	SPI_CPHA_MODE => '0'                -- sample on falling edge when CPOL = '1'
	)
port map (

	clk => clk,
	rst => rst,
	data_in => spi_data_in_i,
	data_out => spi_data_out_i,
	spi_write_req => spi_write_req_i,
	spi_busy => spi_busy_i,
	spi_CPOL => spi_CPOL_i,
	spi_CPHA => spi_CPHA_i,
		
	-- connection to spi device
	SPI_CLK => SPI_clk,
	MISO => SPI_MISO,
	MOSI => SPI_MOSI
    
);

– Clock process definitions

CLOCK_GEN : entity bitvis_vip_clock_generator.clock_generator_vvc
generic map(
	GC_CLOCK_PERIOD    => clk_period,
	GC_CLOCK_HIGH_TIME => clk_period / 2
)
port map(
	clk => clk
); 

start_clock(CLOCK_GENERATOR_VVCT, 1, "Starting clock");

– Stimulus process
stim_proc: process
begin

-- Every UVVM sequencer should start with this procedure call when using VVCs
await_uvvm_initialization(VOID);	

log(ID_LOG_HDR, "Configuring VVCs");

-- access the t_vvc_config for GC_INSTANCE_IDX of the vvc that contains all configuration data for VVC
-- defined in spi_bfm_pkg.

shared_spi_vvc_config(1).bfm_config.CPOL := '0';
shared_spi_vvc_config(1).bfm_config.CPHA := '0';
shared_spi_vvc_config(1).bfm_config.spi_bit_time := 1 ms;

shared_sbi_vvc_config(1).bfm_config.use_ready_signal := false;
shared_sbi_vvc_config(1).bfm_config.clock_period:= 10 ns;
shared_sbi_vvc_config(1).bfm_config.setup_time := 2.5 ns;
shared_sbi_vvc_config(1).bfm_config.hold_time := 2.5 ns;


log( ID_LOG_HDR , "SPI Module- Testbench" );
log( ID_SEQUENCER, "" );

log( ID_LOG_HDR , "do stuff...");


  -- hold reset state for 100 ns.
rst <= '1';	   
wait for 100 ns;	
rst <= '0';

-- Send command to SPI Master
sbi_write(SBI_VVCT, 1, x"1000", x"40", "Set baud rate to 9600");
spi_slave_receive_only(SPI_VVCT, 1, "Receive from Peripheral 1 and store data in VVC to be retrieved by means of fetch_result()");
await_completion(SPI_VVCT, 1, 1 ms, "Wait for SPI Transaction to complete", C_SCOPE);

wait;

end process;

END;

Hi,
You need to put this VVC command inside the testbench sequencer, somewhere after await_uvvm_initialization(VOID);

Br,
Marius

Thank you for pointing that out. I am completely missed it. That seems to have fixed the problem for this particular error.

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