I’ve been experimenting with UVVM. I have managed to run the bitvis_uart example from a makefile, using 3 different free simulators (GHDL, NVC and Questa Intel FPGA Edition).
The makefile is quite simple:
# simulation preferences
SIM_VHDL_RELAXED=TRUE
#SIM_VHDL_SUPPRESS_IEEE_ASSERTS=TRUE
# include here
include ../../contrib/Makefile_UVVM
# source, in compilation order
SRC=\
../src/uart_pkg.vhd \
../src/uart_pif_pkg.vhd \
../src/uart_pif.vhd \
../src/uart_core.vhd \
../src/uart.vhd \
../tb/uart_vvc_demo_th.vhd \
../tb/uart_vvc_demo_tb.vhd
# compile
$(eval $(call COMPILE,bitvis_uart,$(SRC)))
# run simulation
$(eval $(call RUN,uart_vvc_demo_tb,))
The heavy lifting (simulator specific stuff) is done in the include file. My approach assumes precompiled libraries, and takes some advantage of make’s ability to work out what needs doing and what does not, so simulations run quite quickly.
Is anyone interested in this? I could create a pull request to add it to the UVVM repo…
Hi, this is of interest, but could you please add some documentation for this to allow users a brief introduction to the provided functionality and commands. Would be great if you could update your pull request with a simple *.txt file for this purpose.
Hi Espen,
Thanks for accepting this PR and I hope that it helps to promote UVVM to a wider audience. I will keep an eye on your repo for issues with make support and help out where I can. Thankyou to you and your colleagues for creating UVVM.
-Adam
I’ve added Xilinx Vivado simulator (xsim) support to multisim.mk see what would happen. It did not go well! The bitvis_uart example causes xelab to fail silently without generating an executable, and bitvis_irqc fails due to incomplete VHDL-2008 support in xvhdl:
ERROR: [XSIM 43-3246] File C:/work/UVVM/bitvis_irqc/tb/irqc_demo_tb.vhd, line 47. Resolution functions for user-defined types with fields other than std_logic types are not supported. "sbi_if" is such an unsupported multiply driven signal.
In the process I have created a compile_all script that precompiles UVVM for Vivado simulations. I hope that this work may be useful one day, but right now the Vivado simulator seems to be a dead end for UVVM.
I have tried Xilinx XSim 2022.2 with bitvis_uart and it’s still not working. Silent failure during elaboration, after Completed simulation data flow analysis.
In the process, I have created an alternative to ghdl_compile_all_and_simulate.sh. My version works with GHDL, NVC, Questa/ModelSim and (almost) XSim. Would this be of interest?
Hopefully UVVM will soon work with the Xilinx toools.
This sound good. I assume your alternative is a pure superset of the existing version - i.e. only with additional functionality and backwards compatible?
Hi
No problem!
I developed the shell script stuff into a pull request. Take a look. Nothing revolutionary, the idea is to make small improvements to the “first contact” experience.
With a better XSim on the horizon, it might make sense to wait for it to arrive and then iron out any bugs before bringing these scripts into your project?
-Adam
Thanks.
If I understand you correctly, you suggest to wait with this pull request.
It would then be great if you could make an updated pull request once Xilinx has a UVVM and VHDL compliant simulator available.
– Espen
