Driving UVVM simulations using GNU make

I’ve been experimenting with UVVM. I have managed to run the bitvis_uart example from a makefile, using 3 different free simulators (GHDL, NVC and Questa Intel FPGA Edition).

The makefile is quite simple:

# simulation preferences
SIM_VHDL_RELAXED=TRUE
#SIM_VHDL_SUPPRESS_IEEE_ASSERTS=TRUE

# include here
include ../../contrib/Makefile_UVVM

# source, in compilation order
SRC=\
	../src/uart_pkg.vhd		   \
	../src/uart_pif_pkg.vhd    \
	../src/uart_pif.vhd		   \
	../src/uart_core.vhd	   \
	../src/uart.vhd            \
	../tb/uart_vvc_demo_th.vhd \
	../tb/uart_vvc_demo_tb.vhd

# compile
$(eval $(call COMPILE,bitvis_uart,$(SRC)))

# run simulation
$(eval $(call RUN,uart_vvc_demo_tb,))

The heavy lifting (simulator specific stuff) is done in the include file. My approach assumes precompiled libraries, and takes some advantage of make’s ability to work out what needs doing and what does not, so simulations run quite quickly.

Is anyone interested in this? I could create a pull request to add it to the UVVM repo…

Hi, this is of interest, but could you please add some documentation for this to allow users a brief introduction to the provided functionality and commands. Would be great if you could update your pull request with a simple *.txt file for this purpose.

– Espen

Hi Espen
I’ve pushed an update with a MAKE_SUPPORT.md file, take a look and let me know if you would like more detail.
-Adam

Hi Adam,
That looks fine.
Thanks for contributing to a better UVVM.
We will try to get the pull request out as soon as possible.
– Espen

P.S.: This might be of interest to you: GitHub - HDLUtils/hdlregression

Hi Espen,
Thanks for accepting this PR and I hope that it helps to promote UVVM to a wider audience. I will keep an eye on your repo for issues with make support and help out where I can. Thankyou to you and your colleagues for creating UVVM.
-Adam

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Hi Adam,
Thanks, and great that you can follow up on some support on this. :slight_smile:
– Espen

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