Hi everyone! I’m new of UVVM and this is my first experience of verification design; anyway…
I must test (with UVVM framework) one IP. This IP has a simle AXI memory mapped interface (ADDR, DATA, READY, VALID, LEN and STROBE signal). In these days i’m playing with axi BFM interface.
Now my problem. When I try to use axi_write
axi_write(x"0000ffff",x"01",“test”,clk_stimuli,axi_mm_if);
obtain the following error in compile time:
** Error: C:\Users\Enrico\Desktop\smart-dma\tb.vhd(186): (vcom-1600) No feasible entries for subprogram "axi_write".
Visible subprograms are:
(explicit) axi_bfm_pkg.axi_write[STD_LOGIC_VECTOR, UNSIGNED, UNSIGNED, INTEGER, bitvis_vip_axi.axi_bfm_pkg.t_axburst, bitvis_vip_axi.axi_bfm_pkg.t_axlock, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_axprot, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_xresp, std.STANDARD.STRING, STD_LOGIC, bitvis_vip_axi.axi_bfm_pkg.t_axi_if, std.STANDARD.STRING, uvvm_util.adaptations_pkg.t_msg_id_panel, bitvis_vip_axi.axi_bfm_pkg.t_axi_bfm_config] at C:/Users/Enrico/UVVM/script/../bitvis_vip_axi/script/../src/axi_bfm_pkg.vhd(238)
** Error: tb.vhd(250): (vcom-1600) No feasible entries for subprogram "axi_write".
Visible subprograms are:
(explicit) axi_bfm_pkg.axi_write[STD_LOGIC_VECTOR, UNSIGNED, UNSIGNED, INTEGER, bitvis_vip_axi.axi_bfm_pkg.t_axburst, bitvis_vip_axi.axi_bfm_pkg.t_axlock, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_axprot, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_xresp, std.STANDARD.STRING, STD_LOGIC, bitvis_vip_axi.axi_bfm_pkg.t_axi_if, std.STANDARD.STRING, uvvm_util.adaptations_pkg.t_msg_id_panel, bitvis_vip_axi.axi_bfm_pkg.t_axi_bfm_config] at C:/Users/Enrico/UVVM/script/../bitvis_vip_axi/script/../src/axi_bfm_pkg.vhd(238)
** Error: tb.vhd(298): VHDL Compiler exiting
It looks like a casting\overloading problem but I don’t understand where is the problem :-/
I use modelsim 10.6d