Unable to use axi_write in my project

VVC Bitvis VIP AXI
1

Hi everyone! I’m new of UVVM and this is my first experience of verification design; anyway…

I must test (with UVVM framework) one IP. This IP has a simle AXI memory mapped interface (ADDR, DATA, READY, VALID, LEN and STROBE signal). In these days i’m playing with axi BFM interface.

Now my problem. When I try to use axi_write

axi_write(x"0000ffff",x"01",“test”,clk_stimuli,axi_mm_if);

obtain the following error in compile time:

** Error: C:\Users\Enrico\Desktop\smart-dma\tb.vhd(186): (vcom-1600) No feasible entries for subprogram "axi_write".
   Visible subprograms are:
      (explicit) axi_bfm_pkg.axi_write[STD_LOGIC_VECTOR, UNSIGNED, UNSIGNED, INTEGER, bitvis_vip_axi.axi_bfm_pkg.t_axburst, bitvis_vip_axi.axi_bfm_pkg.t_axlock, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_axprot, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_xresp, std.STANDARD.STRING, STD_LOGIC, bitvis_vip_axi.axi_bfm_pkg.t_axi_if, std.STANDARD.STRING, uvvm_util.adaptations_pkg.t_msg_id_panel, bitvis_vip_axi.axi_bfm_pkg.t_axi_bfm_config] at C:/Users/Enrico/UVVM/script/../bitvis_vip_axi/script/../src/axi_bfm_pkg.vhd(238)
** Error: tb.vhd(250): (vcom-1600) No feasible entries for subprogram "axi_write".
   Visible subprograms are:
      (explicit) axi_bfm_pkg.axi_write[STD_LOGIC_VECTOR, UNSIGNED, UNSIGNED, INTEGER, bitvis_vip_axi.axi_bfm_pkg.t_axburst, bitvis_vip_axi.axi_bfm_pkg.t_axlock, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_axprot, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, STD_LOGIC_VECTOR, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, uvvm_util.types_pkg.t_slv_array, STD_LOGIC_VECTOR, bitvis_vip_axi.axi_bfm_pkg.t_xresp, std.STANDARD.STRING, STD_LOGIC, bitvis_vip_axi.axi_bfm_pkg.t_axi_if, std.STANDARD.STRING, uvvm_util.adaptations_pkg.t_msg_id_panel, bitvis_vip_axi.axi_bfm_pkg.t_axi_bfm_config] at C:/Users/Enrico/UVVM/script/../bitvis_vip_axi/script/../src/axi_bfm_pkg.vhd(238)
** Error: tb.vhd(298): VHDL Compiler exiting

It looks like a casting\overloading problem but I don’t understand where is the problem :-/

I use modelsim 10.6d

2

Hi,

It seems like you are missing some parameters in the axi_write() call. You can check the documentation in bitvis_vip_axi/doc/axi_bfm_QuickRef.pdf for more information on the parameters.

3

Hi! Thank you for your reply… At the end I decide to build my “axi” BFM from scratch because the bitvis axi implementation it’s overkilled for my purpose.

I spent about 2-3 working days for coding my BFM (my FIRST BFM)… UVVM looks awesome :smile:

4

Doesn’t work in my project either,

my code is:

axi_write(
  VVCT             => AXI_VVCT,
  vvc_instance_idx => 0,
  awaddr           => unsigned(x"00000000"),
  wdata            => t_slv_array'(x"00000000"),
  msg              => "Testing AXI write"
);

The definition in ./bitvis_vip_axi/src/vvc_methods_pkg.vhd (cloned from Git yesterday) is

procedure axi_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant awid : in std_logic_vector := "";
constant awaddr : in unsigned;
constant awlen : in unsigned(7 downto 0) := (others => '0');
constant awsize : in integer range 1 to 128 := 4;
constant awburst : in t_axburst := INCR;
constant awlock : in t_axlock := NORMAL;
constant awcache : in std_logic_vector(3 downto 0) := (others => '0');
constant awprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA;
constant awqos : in std_logic_vector(3 downto 0) := (others => '0');
constant awregion : in std_logic_vector(3 downto 0) := (others => '0');
constant awuser : in std_logic_vector := "";
constant wdata : in t_slv_array;
constant wstrb : in t_slv_array := C_EMPTY_SLV_ARRAY;
constant wuser : in t_slv_array := C_EMPTY_SLV_ARRAY;
constant bresp_exp : in t_xresp := OKAY;
constant buser_exp : in std_logic_vector := "";
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);

There are only four arguments without default definitions, VVCT, vvc_instance_idx, awaddr and msg. So what is the problem?

Strangely, axi_read compiles OK.

axi_read(
  VVCT             => AXI_VVCT,
  vvc_instance_idx => 0,
  araddr           => unsigned(x"00000000"),
  data_routing     => TO_BUFFER,
  msg              => "Testing AXI read"
);
5

Finally got it working, seems to have something to do with type recognition in the actuals, using Aldec Riviera. The following works:

   variable v_adr_1st         : natural;
   variable v_data_block_1st  : t_slv_array(0 to 255)(31 downto 0);
   variable v_len_1st         : natural;

Begin

  R_TEST: for idx in 0 to 3 generate
   begin
        axi_write(
           VVCT              => AXI_VVCT,
           vvc_instance_idx  => idx,
           awaddr            => to_unsigned(v_adr_1st, 32),
           awid              => std_logic_vector(to_unsigned(idx, 2)),
           awlen             => to_unsigned(v_len_1st, 8),
           wdata             => v_data_block_1st,
           -- awuser            => 1X"00",
           msg               => "1st AXI write"
           );