Hi,
I’m trying to get the exmaple code working.
I have a design which just wires the VVC master signals to the VVC slave
PROBLEM 1
I have defined the signals from the two VVC that drive my design as:
signal axistream_if_driver : t_axistream_if(tdata(C_DATA_WIDTH -1 downto 0),
tkeep((C_DATA_WIDTH/8)-1 downto 0),
tuser(C_USER_WIDTH -1 downto 0),
tstrb((C_DATA_WIDTH/8)-1 downto 0),
tid(C_ID_WIDTH-1 downto 0),
tdest(C_DEST_WIDTH-1 downto 0)
);
signal axistream_if_monitor: t_axistream_if(tdata(C_DATA_WIDTH -1 downto 0),
tkeep((C_DATA_WIDTH/8)-1 downto 0),
tuser(C_USER_WIDTH -1 downto 0),
tstrb((C_DATA_WIDTH/8)-1 downto 0),
tid(C_ID_WIDTH-1 downto 0),
tdest(C_DEST_WIDTH-1 downto 0)
);
p_main: process
v_data_array : t_slv_array (0 to 9) (31 downto 0);
v_exp_data_array : t_slv_array (0 to 9) (31 downto 0);
...
begin
-- copy of vvc quick ref page 4
axistream_transmit(AXISTREAM_VVCT, 0, v_data_array(0 to 1),
“Send a 2 byte packet to DUT, tuser=0 each word / clock cycle”, C_SCOPE);
-- copy of vvc quick ref page 4 and 5
axistream_expect(AXISTREAM_VVCT, 1, v_exp_data_array(0 to 1),
“Expect a 2 byte packet, ignoring the tuser bits”, C_SCOPE);
await_completion (AXISTREAM_VVCT, 0, 10 * C_AXI_CLOCK);
end process;
This gives an error in QuestaSim
No feasible entries for axistream_expect
PROBLEM 2
If I don’t use axistream_expect but
-- copy of vvc quick ref page 5
axistream_receive(AXISTREAM_VVCT, 1, “Receive data to VVC”, C_SCOPE);
I don’t get an error in QuestaSim
But in they waveform I see the VVC slave doesn’t respond.
For example the t_ready from the slave VVC side is never driven.
What else should I do that is not in the example code of the document
Rgds,
Eric