I have an entity whose interfaces are UART and AXI LITE Master. I managed to simulate the UART interfaces TX and RX with UVVM, but I am not able to set an AXI LITE VVC as slave connected to my Master interface.
Should I be able to do that? Am I missing something?
Thanks in advance
Unfortunately there is no slave support for the AXI Lite VVC at the moment. We see the need for a slave VVC and plan to include this in a future release. Meanwhile we hope that someone in the community can contribute with a pull-request or provide it as a VIP in the UVVM Community VIPs repository.