How to create two independent VVC master to stream data

VVC Bitvis VIP AXI-Stream
1

Hi,

I’m using the standard way of creating the “p_main” procedure

------------------------------------------------
p_main: process
  ...
begin
  ...
  -- Finish the simulation
  std.env.stop;
end process p_main;
------------------------------------------------

How can I make this testbench so that I have two axi-streaming drivers that are sending data on their own clock?

Say for example I have an axi-stream arbitter of two incomming streams with different speed and different lengths. How can I include these processes? Something like this?

pseudo:

process1 (clk of 10 ns)
     enable input from p_main to start?
     for 1 to 10
     axistream_transmit(AXISTREAM_VVCT, C_ID_DRV1_SAXI, v_sample(0 to 9), "Send 10 100 MHz) samples ", C_SCOPE);
     end for
     wait ? or signal to p_main done?
end process1;

process2 (clk of 33 ns)
     enable input from p_main to start?
     for 1 to 5
     axistream_transmit(AXISTREAM_VVCT, C_ID_DRV2_SAXI, v_sample(0 to 99), "Send 100 33 MHz) samples ", C_SCOPE);
    end for
     wait ? or signal to p_main done?
end process2;

------------------------------------------------
p_main: process
  ...
begin
  ...
  enable process1
  enable process2
  ...
  wait on done from process1 
  wait on done from process2
  ...
  -- Finish the simulation
  std.env.stop;
end process p_main;
------------------------------------------------
2

Hi,

As you are already using VVCs, it is dead simple to control them - even from one single sequencer if you like.
Your approach is perfectly OK, but you could in fact also put both your three-line for-loops directly into p_main. The order would not matter as you are just telling the VVCs in zero-time to set up 10 and 5 transmissions respectively. Processes 1 and 2 would then not be needed, and the two waits in p_main could be replaced by two await_completion() commands (also in any order).

– Espen