Best practices when combining assertion based testing with UVVM

Hi, I was wondering what is the best practice when combining assertion based tests with UVVM? Typically I want to have the assertions in a separate process which is sensitive to tb_clk.

I could make such a process in the test harness (th.vhd), but I feel that the test harness should be reserved for connections between the test bench and DUT. Am I correct?

I do not want to create a separate process in the test bench (tb.vhd), as I only want the process to fire when tb_clk changes to reduce simulation time. To my knowledge, VHDL-08 does not support aliases for input signals of processes, to allow that.

I cannot create a process within the main process in tb.vhd, as VHDL does not support nested processes as far as I know.

Hi, I am not 100% certain I have understood your question correctly, but let me try to answer.
We use assertion based testing a lot, - with VHDL processes rather than PSL or SVA, as our customers often do not have licenses for PSL or SVA.
I guess there is a lot of “religion” when it comes to how testbenches should be organised, but in my opinion the most important issues are understanding/readability, maintainability and reuse.
I don’t see any problem in having assertions in the test harness as long as these assertions are checking behaviour of functionality and signals available there. I would much prefer to have the assertion there rather than in the test bench (assuming now that the testbench architecture is implemented primarily in the test harness).
You could of course add another process inside your test bench, but in my opinion most types of assertions would belong in the test harness;- again depending on your architecture.
If you are making your own verification components, you could also include assertions inside these. Assertions inside your design could also be very efficient, but you might have to exclude these from synthesis.
BTW - implementing VHDL assertions as concurrent procedures is recommendable if reuse is wanted.

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Thanks for your reply. You understood my question correctly.

I am adding my own VVCs and will be adding assertions regarding the interfaces to them. My testbench architecture is indeed implemented in the test harness and I will add other assertions there.

To comply with a project specific standard, I am not allowed to add any lines of code to the design (DUT), but thanks for the tips.