Test bench hangs up on wait statement

I am running a simulation that requires a monitor to wait for one second to initialize. I tried using a wait statement in my test case, but if I wait more than 10 ms the simulator hangs on that step. I’m using Questasim 10.7c. Any help would be appreciated.

***I finally was patient enough to wait and it took 45 seconds for the TB to wait 20 ms. Any reason? Thanks

It’s difficult for us to know how much time it should take to wait for 20 ms simulation time. We have very simple testcases where this could take less than a second, but we also have larger testcases where this could take many hours. This is normally mainly dependent on the design you are verifying. Without knowledge on that it is difficult to give any advice.

  • Espen

Thanks for your reply EspenT, I am new to UVVM and verification in general. I am trying to test a CPLD with Arinc and SERDES and a few discretes. The problem is the test bench sequencer runs faster that the code responds due to design delay. I cannot change the design code so I wanted to make the test bench wait for a certain time or signal. When I use ‘wait until (condition) for X ns;’ the test bench hangs up or it causes errors in the following tests. Is there a better way to accomplish this?

It is very difficult to answer that when I don’t have the full overview, but normally it shouldn’t be a problem to align the testbench to the design. If however you need to control several interfaces on a DUT at the same time, then a “normal” testbench could have problems as a single process can only do one thing at a time. If this is a challenge, then moving to VVCs would solve it, but if you are new to verification I would recommend learning how to use the Utility Library and BFMs first.

a good starting point can be to look at the demo testbenches in the UVVM and UVVM_Light repositories:

Read through the testbench sequencer code while having the Utility Library quick reference available, which you can download from here: https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/util_quick_ref.pdf
You will see that the testbench sequencer is “stalled” using “await_…()” procedures while waiting for DUT updates.
There are several other demo testbenches demonstrating more advanced UVVM features, such as VVCs, Scoreboard, Monitors etc.

Best regards,

Thanks for your reply, Marius. I am having to learn how to insert delay, make the sequencer wait, etc. Right now I am just using a loop that reports every 10 ms. This gets long when you have to wait a second. I will check your references.