I would like some advice on including my Sequencer (GEN) in the VVC.
I created a multiple verification components for 30 busses using UVVM light a few years ago. I appreciate how easy it was to get started and how quick creating all the components needed for a bus protocol. The company had many legacy busses and protocols but fortunately many were similar. The verification components created included; Bus Functional Models (BFM), Checkers (CHK), Monitors (MON) and Generators (GEN). The GEN is similar to the UVM Sequencer and was a means of creating framing for the different packets. The GEN is a zero simulation time package similar to the packages used for BFM. A good example was the Ethernet Busses used that included; Ethernet, IP, UDP, TS and two proprietary UDP payloads.
I am going to implement the VVC for the verification library and would like to use all the GEN components. My idea is to place the GEN right before the BFM in the VVC as was done in the TB using UVVM light. I started with a bus used with the UART and have some code to share (with name change and stripped out code). The testing approach is direct wrt the packet fields.
– uart_tx_vvc.vhd
entity uart_tx_vvc is
generic(…
);
port(
–gen
teri_gen_config : in t_gen_config
:= C_GEN_CONFIG_DEFAULT; – config of data in payload
teri_gen_config_teri : in t_teri_config
:= C_teri_CONFIG_DEFAULT; – config of teri packet specs
teri_gen_config_teri_header : in t_teri_header_config
:= C_teri_HEADER_CONFIG_DEFAULT; – data in header field
teri_gen_config_teri_message : in t_teri_message_config
:= C_teri_MESSAGE_CONFIG_DEFAULT; --data in message field
teri_gen_config_teri_trailer : in t_teri_trailer_config
:= C_teri_TRAILER_CONFIG_DEFAULT; – data in trailer field
–bfm
uart_vvc_tx : inout std_logic := GC_UART_CONFIG.idle_state
);
end entity uart_tx_vvc;
teri_gen_teri_pkt ( gen_data => var_gen_data,
config => teri_gen_config,
config_teri => teri_gen_config_teri,
config_teri_header => teri_gen_config_teri_header,
config_teri_message => teri_gen_config_teri_message,
config_teri_trailer => teri_gen_config_teri_trailer
);
uart_transmit(data_value => var_gen_data,
msg => format_msg(v_cmd),
tx => uart_vvc_tx,
config => v_vvc_config_copy.bfm_config,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);