Level of protocol compliance of various VVC's components provided in UVVM


UVVM provides various VVC components that can be used out of the box.
For example Avalon MM, AXI-lite, AXI-stream, SPI, ect.
To which level of protocol compliances are these specified and tested?
Is this somewhere in the VVC documentation?

For example:

Is the Avalon MM VVC fully compliant to the Avalon specification of Intel/Altera?
Does the Avalon MM VVC support burst mode?
Does the Avalon MM VVC respect the WAIT_REQUEST signal?
Where can I find which SPI MODEs are all supported in the SPI VVC?

I can also imagine that not all features are implemented, as this is protocol specific.
And UVVM is not a Verification IP provider, but an open source verification methodology.
So what is the UVVM/bitvis philosophy behind creating and providing VVC components?
Is it just a “getting started component with basic/limited protocol features”?
Or something else as well?


Hi Eric,

First of all, the BFMs and VVCs (which are also using BFMs towards the interface) are not protocol checkers. A protocol checker is far more complex and also requires more from the user.

UVVM BFMs (and thus also VVCs) are interface access models (transaction level models) that allow users to access interfaces at a high level – using simple to understand procedures.

The VVCs in addition allow parallel access to multiple interfaces in a structured manner from a single test sequencer (or multiple sequencers if you like, but that is more error prone). Some VVCs also have some protocol checker capabilities, like error injection, random valid/ready activation, etc, but they are not full protocol compliance checkers.

You will have to check for every BFM/VVC what features have been implemented. This differs from model to model, but should be easy to see from the provided BFM and VVC documentation.