I worked on building a library or UVVM components for 30+ bus protocols for a company a few years ago using the UVVM light. The effort went well and the different Bus Functional Models, Checkers, Monitors were relatively easy to implement. I appreciate UVVM. The team of new VHDL engineers use the library quickly.
During this effort an additional block was created that is similar to the UVM Sequencer in the UVM Agent. This VHDL package is named Generate and performs the framing up of many protocol including; Ethernet, IP, UDP, and TS.
Now I would like to upgrade to using VVC and still use the verification components GEN, BFM ,MON, CHK. Can I place the GEN procedure call before the BFM procedure call in the VVC? Any thoughts on how to implement would be appreciated.