Sorry, I had to split the post and remove the links because of the weird restriction for new users
Hello UVVM developers,
I am maintaining a build system for hardware projects called SoCMake, it is built on top of CMake, and the main advantage compared to other open-source build systems is the C/C++ native support.
I started developing SoCMake while working at CERN, and it is still currently used there.
SoCMake supports common HDL languages Verilog, SystemVerilog, and VHDL.
SoCMake also supports RTL simulators such as Verilator, GHDL, Icarus Verilog, Vivado simulator, Xcelium, Questasim, Modelsim, and VCS.
I recently packaged UVVM as a SoCMake IP library so that it can be easily reused in SoCMake projects.
The git repository can be found here: UVVM_SoCMake:
Here is a short demo of simulating the uart_vvc_demo_tb example:
cmake_minimum_required(VERSION 3.25)
project(uart_vvc_demo_tb NONE)
###############################################
############ Package management ###############
###############################################
# Include CPM package manager, otherwise you can use built in FetchContent
include("../../deps/CPM.cmake")
# Fetch SoCMake
CPMAddPackage(
NAME SoCMake
GIT_TAG develop
GIT_REPOSITORY "https://github.com/HEP-SoC/SoCMake.git"
)
CPMAddPackage(NAME uvvm_socmake
GIT_REPOSITORY https://github.com/HEP-SoC/UVVM_SoCMake.git
GIT_TAG master
OPTIONS
"UVVM_VERSION v2_2024.10.23"
# Decide which libraries to include from UVVM
"UVVM_INCLUDE_BITVIS_VIP_SBI ON"
"UVVM_INCLUDE_BITVIS_VIP_UART ON"
"UVVM_INCLUDE_BITVIS_UART ON"
"UVVM_INCLUDE_BITVIS_VIP_CLOCK_GENERATOR ON"
)
###############################################
############ CLI options ######################
###############################################
# Pass these options with -D<option>=<value> with cmake call, or through cmake-gui
option_enum(SIMULATOR "Which simulator to use" "ghdl;questa;modelsim;vivado_sim;all" "ghdl")
if(SIMULATOR STREQUAL "all")
set(ALL_SIMS TRUE)
endif()
# Add IP for the uart demo project
add_ip(${PROJECT_NAME}
LIBRARY bitvis_uart)
# Include demo testbench sources
ip_sources(${IP} VHDL
./uart_vvc_demo_th.vhd
./uart_vvc_demo_tb.vhd
)
ip_link(${IP}
uvvm::bitvis_vip_sbi::vip
uvvm::bitvis_vip_uart::vip
uvvm::bitvis_uart::uart
uvvm::bitvis_vip_clock_generator::vip
)
if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
modelsim(${IP} VCOM_ARGS -2008 -suppress 1346,1236)
endif()
if(SIMULATOR STREQUAL "vivado_sim" OR ALL_SIMS)
vivado_sim(${IP}
XVHDL_ARGS --2008 --relax
XELAB_ARGS --relax
)
endif()
if(SIMULATOR STREQUAL "ghdl" OR ALL_SIMS)
ghdl(${IP}
STANDARD 08
ANALYZE_ARGS -frelaxed-rules -Wno-hide -Wno-shared
ELABORATE_ARGS -frelaxed-rules
)
endif()
help()
As you can see SoCMake is capable of downloading UVVM from the GIT repository, and “linking” the UVVM libraries into user testbench.
From there Make targets for Modelsim/Questasim, GHDL and Vivado simulator can be created.
On top of that using CTest, we can create a regression to run all the available tests for the testbench (as done in SV-UVM example)
SoCMake can also generate a Graphviz dot file of the build graph, to easier understand the dependencies of the build flow, as shown in the figure below:
To better understand how SoCMake works, here is a quick explanation of IP libraries:
IP libraries are the basic building blocks in SoCMake, and they represent an IP that contains some files and properties.
In this case, we are creating bitvis_vip_avalon_st UVVM library.
add_ip(uvvm::bitvis_vip_avalon_st::vip::0.0.1)
After that we associate VHDL sources with the library.
Currently UVVM_SoCMake is a separate Git repository that fetches the real UVVM repository and provides a supporting CMakeLists.txt file that defines all the UVVM libraries.
If fully integrated each UVVM library subdirectory would contain a CMakeLists.txt file that creates the corresponding library.
If you are interested in seeing how SoCMake integration into UVVM would look, let me know and I can create a fork.
I have 1 additional question regarding simulator support.
I can easily create compilation targets for Xcelium and VCS, however when I try to compile UVVM with these simulators, I get many errors.
I assume that some of the constructs are not supported in Xcelium and VCS.
Did anyone try to support one of these 2 simulators?
If you want to learn more about SoCMake, take a look at this presentation:
To test this, you will need: CMake > 3.25 GHDL Make
Execute the following commands:
git clone https://github.com/HEP-SoC/UVVM_SoCMake.git
cd UVVM_SoCMake/examples/uart/
mkdir build && cd build
cmake ../
make run_bitvis_uart__uart_vvc_demo_tb_ghdl