A very simple testbench using four bitvis_vip_axi.axi_vvc instances aborts a t time zero due to too many delta cycles, probably an infinite loop somewhere without a wait statement.
KERNEL: Stopped at time 0 ps + 5000.
KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
The testbench doesn’t do anything (yet), I just want to check whether elaboration is successful (it is) and see that clock and reset run OK. The test process is:
process
begin
await_uvvm_initialization(VOID);
insert_delay(AXI_VVCT,0 , 50 ns, "50 ns delay", C_SCOPE);
insert_delay(AXI_VVCT,1 , 50 ns, "50 ns delay", C_SCOPE);
insert_delay(AXI_VVCT,2 , 50 ns, "50 ns delay", C_SCOPE);
insert_delay(AXI_VVCT,3 , 50 ns, "50 ns delay", C_SCOPE);
wait;
end process;