Multiple I2C slave devices on the same lines

VVC Bitvis VIP I2C
1

Hi

In my hardware design, I have two i2c slave components connected to the same i2c lines, and I would like to simulate with the same architecture.
I put 2 I2C_VVC in my design, configured as slaves, connected to the same sda and scl lines. My problem occurs when my master sends data to one of the vvc while the other is already waiting for value. The testbench fires a failure, while the behavior is normal.

I tried putting slave_mode_address_severity to NOTE, but then I have to wait for a transfer again. Is there a way to just ignore when the address received is not for the slave, and the same slave still continues to wait for a transfer without the need of starting a new wait instruction (i2c_slave_receive or i2c_slave_check)?

Or maybe my testbench architecture is not the best way to test this hardware configuration, and would be happy to hear improvements.

2

Hi,

If we understand you correctly, are you trying to to the following:
Set up both slaves to receive on separate addresses - using e.g. i2c_slave_check()
Then transmit a frame with a given address and expect that
a) slave 1 with a matching address checks the received data AND
b) slave 2 with a nonmatching address ignores the frame completely as if it was never received - and is thus ready to check the next incoming frame without the need for a new check command.
Would be great if you could comment on this?

Regards UVVM team