Problem with Questa 2019.2?

1

I am a complete newbie to UVVM. I am playing with it to decide if this is the way to go or is OSVVM better. I tried to run a simple simulation using Questa 2019.2. I created a sim directory in the bitvis_uart design and ran the simulato from there with the “do …/script/compile_all_and simulate.do”. It compiles and the design starts to load and then I get a fatal

Loading bitvis_vip_scoreboard.generic_sb_pkg(body)

** Fatal: Internal error: …/…/src/vsim/rtu.c (4724)

Time: 0 ns Iteration: 0 Region: /generic_sb_pkg File: …/…/bitvis_vip_scoreboard/script/…/src/generic_sb_pkg.vhd Line: 2479

FATAL ERROR while loading design

Error loading design

Error: Error loading design

Pausing macro execution

MACRO ./…/script/simulate_demo_tb.do PAUSED at line 16

Can anyone tell me what is causing this and is there a work around? Thanks so much.

2

I think this might be an issue with this specific Questa version, see Tool Compatibility — UVVM documentation

3

Thank you Erick. I downloaded the 2024 version and the simulations work fine.

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