Inexplicable behavior of the AXI-Lite VIP in Modelsim

Hi all,

I tried to use the latest AXI-Lite VIP in Modelsim (2020.4), but now I’m already stuck when starting the simulator.
A short info:
I already use the previous VIP and everything has worked flawlessly so far. I wanted to switch to the new version, but now I have the problem that Modelsim stops loading the design with the following error:

# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ns Iteration: 0 Process: / test_tb / axilite_vvc_1 / read_address_channel_executor File: V:/UVVM /script/../bitvis_vip_axilite/script/../src/axilite_vvc.vhd
# FATAL ERROR while loading design

In my test bench, which leads to this error, only the AXI-Lite VCC is instantiated, nothing else. If I start the AXI-Lite VCC component itself directly from its library, Modelsim loads without any problems. I cannot explain the current behavior, because apparently all necessary components have been compiled correctly and should be available.

It would be great if you could help me on this matter.
Thank you.

are you running with Mentor Modelsim or another simulator?


Hi Marius,

I use ModelSim DE-64 2020.4.

Best regards


here is some additional information.
I have observed this problem with the AXI Lite VIP version 2.8.0.
Since I’ve now gone back to version 2.7.1, everything works fine.

Best regards

Hi, I have also experienced this bug with the AXI VIP. Could not find any fix yet. I am using Modelsim DE 10.6b.

Hi all,

I also could reproduce the same behavior with the latest AXI Lite VIP (2.8.1).

When I start the test bench with

vsim tb_lib.test_tb

the error occurs.

# Loading uvvm_vvc_framework.ti_uvvm_engine(func)
# Loading bitvis_vip_axilite.axilite_vvc(behave)
# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ns  Iteration: 0  Process: /test_tb/axilite_vvc_1/read_address_channel_executor File: D:/tmp/uvvm_test/axilite/uvvm/script/../bitvis_vip_axilite/script/../src/axilite_vvc.vhd
# FATAL ERROR while loading design
# Error loading design

Contrary, starting the AXI Lite VIP alone with

vsim bitvis_vip_axilite.axilite_vvc

Modelsim loads without any problems.

Maybe this input can help to solve this issue.

Thanks & best regards

Thank you for the extended information.
I will have to test with a DE version and do some debugging. - will notify you when I have a fix.


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We have found a workaround for this issue. It will be included in the next release.

This issue has also been reported earlier. See where you can also find example code that can be used until the next release.


Hi Jørgen,
hi all,

thank you for your efforts and your great support.
I exchanged the two files you mentioned, and now I can get my simulation successfully started.

Thanks for your help and your great work you all are doing!

Best regards

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