Inexplicable behavior of the AXI-Lite VIP in Modelsim

VVC Bitvis VIP AXI-Lite
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1

Hi all,

I tried to use the latest AXI-Lite VIP in Modelsim (2020.4), but now I’m already stuck when starting the simulator.
A short info:
I already use the previous VIP and everything has worked flawlessly so far. I wanted to switch to the new version, but now I have the problem that Modelsim stops loading the design with the following error:

# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ns Iteration: 0 Process: / test_tb / axilite_vvc_1 / read_address_channel_executor File: V:/UVVM /script/../bitvis_vip_axilite/script/../src/axilite_vvc.vhd
# FATAL ERROR while loading design

In my test bench, which leads to this error, only the AXI-Lite VCC is instantiated, nothing else. If I start the AXI-Lite VCC component itself directly from its library, Modelsim loads without any problems. I cannot explain the current behavior, because apparently all necessary components have been compiled correctly and should be available.

axilite_tb
axilite_tb861×888 157 KB

It would be great if you could help me on this matter.
Thank you.

2

Hi,
are you running with Mentor Modelsim or another simulator?

Br
Marius

3

Hi Marius,

I use ModelSim DE-64 2020.4.

Best regards

4

Hello,

here is some additional information.
I have observed this problem with the AXI Lite VIP version 2.8.0.
Since I’ve now gone back to version 2.7.1, everything works fine.

Best regards

5

Hi, I have also experienced this bug with the AXI VIP. Could not find any fix yet. I am using Modelsim DE 10.6b.

6

Hi all,

I also could reproduce the same behavior with the latest AXI Lite VIP (2.8.1).

When I start the test bench with

vsim tb_lib.test_tb

the error occurs.

...
# Loading uvvm_vvc_framework.ti_uvvm_engine(func)
# Loading bitvis_vip_axilite.axilite_vvc(behave)
# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ns  Iteration: 0  Process: /test_tb/axilite_vvc_1/read_address_channel_executor File: D:/tmp/uvvm_test/axilite/uvvm/script/../bitvis_vip_axilite/script/../src/axilite_vvc.vhd
# FATAL ERROR while loading design
# Error loading design
...

Contrary, starting the AXI Lite VIP alone with

vsim bitvis_vip_axilite.axilite_vvc

Modelsim loads without any problems.

Maybe this input can help to solve this issue.

Thanks & best regards

7

Thank you for the extended information.
I will have to test with a DE version and do some debugging. - will notify you when I have a fix.

Br,
Marius

1 Like
8

Hi,

We have found a workaround for this issue. It will be included in the next release.

This issue has also been reported earlier. See https://github.com/UVVM/UVVM/issues/118 where you can also find example code that can be used until the next release.

Regards,
Jørgen

9

Hi Jørgen,
hi all,

thank you for your efforts and your great support.
I exchanged the two files you mentioned, and now I can get my simulation successfully started.

Thanks for your help and your great work you all are doing!

Best regards

1 Like