How to use uart_expect()?

Hi, I am a newbie to use the UVVM_Lite for my verification. I met an question is how to use the uart_expect or uart_receive, I use it like this:

-- UART Internal Procedures   
        procedure uart_expect (
            constant data_exp           : in std_logic_vector;
            constant msg                : in string) is 
            uart_expect (
                data_exp        => data_exp,
                msg             => msg,
                rx              => tx_o,
                terminate_loop  => terminate_loop,
                max_receptions  => 1,
                timeout         => -1 ns,
                alert_level     => ERROR,
                config          => uart_bfm_config,
                scope           => C_SCOPE,
                msg_id_panel    => shared_msg_id_panel
for i in 0 to 255 loop 
        v_data_exp  := std_logic_vector(to_unsigned(i,8));
        --wait for 1 ps;
        --wait for 2*c_clkperiod;
        wait for 1 ps;
        --wait for 2*c_clkperiod;
    end loop;   

But the simulation is FAILURE and the log like this:

UVVM: =========================================================================================================================================================================
UVVM: ***  FAILURE #1  ***
UVVM:          7752 ns   TB seq.
UVVM:                    check_value() => Failed. std_logic  Was '0'. Expected '1'
UVVM:                    uart_expect(x"00") while executing uart_receive. Bus was active when trying to receive data. 
UVVM: Simulator has been paused as requested after 1 FAILURE
UVVM: *** To find the root cause of this alert, step out the HDL calling stack in your simulator. ***
UVVM: *** For example, step out until you reach the call from the test sequencer. ***
UVVM: =========================================================================================================================================================================

Could anybody give me same addvice?
thanks in advance!

The uart_expect() is an uart_receive() where you tell which value you expect to receive. An alert is raised if the received value does not match the expected.
Can you show the testbench setup, sequencer and more of the transcript? Does the simulation stop on the first loop iteration?


Hi Marius,
Sorry for my reply is too late. The question has been solved after I have spent more hours to debug it. but thanks for your help.