Hallo,
how do I tell to my testbench to pipeline the transcations with a single command ? Currently I use the await_completion(…) command after every axi_write or axi_read. Is there a way to tell the VVC to always carry out pipelined transactions?
Thanks!!
Hi,
The VVC will always carry out pipelined commands as soon as possible. I.e. as soon as something makes time pass. This could be an await_completion() as you mentioned, but could also be a normal VHDL wait statement, or any other time consuming command.
There is currently no single command available to do say an axi_write() automatically followed by an await_completion().
You could of course make your own overload or dedicated procedures to do exactly that.
If however, this is something that is generally wanted by the UVVM community, this could be evaluated as an extension to UVVM itself.