Hi Erick,
when i use a keyword called random it will give the random data. when i do multiple runs of simulation it is generating the same data every time. How can I get a different set of data at every time when I run the simulation?
In UVM we have an option of driving the seed from the makefile, do we have something similar here
Best Regards,
Hi Riyaz,
I have moved this question to a new topic since it is not related to VVCs read back.
In UVVM there is the randomize() function you can use to set the global seeds in your testbench. You can find more information on this in the util_quick_ref.pdf under uvvm_util\doc.
Best Regards,
Erick
Hi Erick,
thanks for moving it into a new thread
a_in := random(a_in'length);
b_in := random(b_in'length);
opp := random(1,3);
I used the random function as above, but the type of inputs that are being generated was the same at each and every run. how can I get a different set of data for when I run it every time is my question?
Best Regards,
Riyaz
You can use the randomize function like I mentioned to change the global seeds on each run. You could use a generic for instance.
randomize(GC_SEED1, GC_SEED2, “Setting global seeds”);
a_in := random(a_in’length);
b_in := random(b_in’length);
opp := random(1,3);
Best Regards,
Erick
so this GC_SEED1, GC_SEED2 are generic constants, right?
so i need to update these in my test case or i should need to drive from somewhere
like makefile or do-file
Best Regards,
Riyaz
Yes, you can drive them from your do-file when you start the simulation, e.g.
vsim -gGC_SEED1=12 -gGC_SEED2=14 …
Best Regards,
Erick
yeah i did this but the data which is generating is the same throughout the simulation
there is no change in the data from the start to the end of the simulation
Best Regards,
Riyaz
But are you changing the seeds in the do-file every time you run it?
I just made a quick test and I get different results:
RUN 1:
Best Regards,
Erick
i did it as follows
constant GC_SEED1 : integer := 10;
constant GC_SEED2 : integer := 15;
begin
p_main: process
begin
for i in 0 to 10 loop
randomize(GC_SEED1, GC_SEED2, “Setting Global Seeds”);
a_in := random(a_in’length);
b_in := random(b_in’length);
opp := random(1,3);
alu_write(ALU_INTF_VVCT,1,a_in,b_in,std_logic_vector(to_signed(opp,3)),‘1’,“Writing the data”, C_SCOPE);
alu_read(ALU_INTF_VVCT,1,“input data result”, C_SCOPE);
v_cmd_idx := get_last_received_cmd_idx(ALU_INTF_VVCT, 1);
await_completion(ALU_INTF_VVCT,1,150 ns); – this waits for all VVC cmds to finish
fetch_result(ALU_INTF_VVCT,1, v_cmd_idx, v_result, “Fetching result from read operation”);
wait for 10 ns;
end loop;
I did it like this for the fist run then changed the values again and ran but I didn’t get like you
can you tell me how to add my snapshot also like this I am unable to share it
Best Regards
Riyaz,
You are re-initializing the seeds on every iteration, therefore you get the same values.
The randomize() function should be placed outside the loop and run only once as the purpose is to set an initial value for the global seeds, after that the seeds will get updated with every call to the random() function.
You can just copy the snapshot directly into the reply box or upload an image.
Best Regards,
Erick
Hi Erick,
I used this command to simulate my design
vsim -gui work.alu_demo_tb -voptargs="+acc" -quiet -suppress 12110 -do "wave_sanity.do" -do "log -r /*; run -all" -gGC_SEED2=14 -gGC_SEED1=12
I used this command in makefile it is working for me now
vsim -sv_seed random -gui -debugDB RX1_tb -assertdebug -do wave.do -do "log -r /*; run -all"
This command is used in System Verilog to run the simulation, where every time you call this command the seed value will also get generated randomly because of the keyword random
do we also have something like this which will do the random generation of seed values form the command line itself?
Best Regards,
Riyaz
I don’t think so, at least this is outside the scope of UVVM.
Best Regards,
Erick