The AXI BFM seams to return ‘X’ on read if there is zero hold time of the input data (coming from a slave DUT). The simulation is run using the Xilinx axi_emc IP.
Line 859 of axi_bfm_pkg.vhd waits for a rising edge of the clock
Response values are collected starting at line 867. At this point in time (with zero hold time) the data is not longer valid (see the screenshot). Note: this is from a behavioral simulation, a post synthesis simulation would always show some (minimal) hold time.
Did somebody else run into this issue?
Should here be an independant response sampleing process that will be used as the response ‘source’?