Error in simulation, but waveform is correct

Utility Library
1

Hi,

I have a following problem.

I verify correctness of a low active reset pulse (with Questa):

await_value(lmk_resetn, '0', 0 ns, 100 ns, "Wait for reset to activate");
await_stable(lmk_resetn, 30 ns, FROM_NOW, 60 ns, FROM_NOW, "The reset must be held for 30 ns to have an effect");
await_value(lmk_resetn, '1', 0 ns, 40 ns, "The reset must be released shortly");

Th waveform look fine (10 ns scale):

image

But await_stable misses the rising edge:

# UVVM: ID_POS_ACK                     61620.0 ns  TB seq.                        await_value(sl, 0, 0 ns, 100 ns) => OK. Condition occurred after 20 ns. 'Wait for reset to activate'
# UVVM: ID_POS_ACK                     61650.0 ns  TB seq.                        await_stable(sl, 30 ns, 60 ns) => OK. Condition occurred after 30 ns. 'The reset must be held
# UVVM:                                                                           for 30 ns to have an effect'
# UVVM: 
# UVVM: =========================================================================================================================================================================
# UVVM: ***  ERROR #1  ***
# UVVM:         61690 ns   TB seq.
# UVVM:                    await_value(sl, 1, 0 ns, 40 ns) => Failed. Timed out after 40 ns. 'The reset must be released shortly'
# UVVM: =========================================================================================================================================================================

what could cause this problem?

2

Hi,

Is it possible for you to share your code and TB so that we can have a look?

Br.

Marius

3

It’s not secret but there wpuld be significant difficulties with replicating the simulation:

  1. The code is developed in Vivado but I simulate with Questa One. Vivado doesn’t support Questa One, so I use own script from inside Vivado to start the simulation in order to make use of Vivado’s facilities to get all necessary sources, including generated by Vivado.
  2. The design makes use of VHDL-2019 interfaces (mode views). Questa’s support for them is currently seriously flawed. As workaround I had to create a separate simulation version which inlines all procedures operating on the interface, which turns the design code into barely comprehensible monstrosity