UVVM v2 2020.04.20 is release - with a new VIP

We have release a new version of UVVM:

  • added selection of basic or advanced VVC when generating with vvc_generator.py script
  • added more section with transaction info usage to UVVM VVC Framework Essential Mechanisms pdf.
  • added Bitvis VIP Spec Cov - a brand new VIP for documenting specification coverage in projects.

and several small improvements. Available now from GitHub - UVVM/UVVM: UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/