Can the GC_DEFAULT_LINE_VALUE be a single character instead of needing to be the same amount of characters as the GC_DATA_WIDTH. This currently breaks my attempt to generalize the instantitation of the GPIO.
With NR_OF_LEDS I try to generalise the GPIO. NR_OF_LEDS = 4 in this case. I need to write “ZZZZ” to GC_DEFAULT_LINE_VALUE get this code to work.
If I do that then Modelsim gives an error:
** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 0 (-1 downto 0 (null array)).
Your workaround works.
The normal expected VHDL construct doesn’t.
See here below the code I used to test it.
Find here the example code:
test harness:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_gpio;
use bitvis_vip_gpio.gpio_bfm_pkg.all;
library bitvis_vip_clock_generator;
library lib_front_panel_led;
-- Test harness entity
entity th_test is
generic(
NR_OF_LEDS : natural := 4
);
end entity th_test;
-- Test harness architecture
architecture struct of th_test is
signal leds_green : std_logic_vector(NR_OF_LEDS-1 downto 0);
constant C_DEFAULT_LINE_VALUE : std_logic_vector(NR_OF_LEDS-1 downto 0) := (others => 'Z');
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
i_gpio_green_vvc: entity bitvis_vip_gpio.gpio_vvc
generic map(
GC_INSTANCE_IDX => 1,
GC_DATA_WIDTH => NR_OF_LEDS,
GC_DEFAULT_LINE_VALUE => C_DEFAULT_LINE_VALUE --working construct
--GC_DEFAULT_LINE_VALUE => "ZZZZ" --working construct
-- GC_DEFAULT_LINE_VALUE => (others => 'Z') --failing construct
--** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 0 (-1 downto 0 (null array)).
--# Time: 0 ps Iteration: 0 Instance: /tb_test/i_th_harness/i_gpio_green_vvc File: C:/repos/SCB_EXE_SW/uvvm/uvvm/script/../bitvis_vip_gpio/script/../src/gpio_vvc.vhd Line: 45
--# FATAL ERROR while loading design
)
port map(
gpio_vvc_if => leds_green
);
end struct;
And here the testbench:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_gpio;
use bitvis_vip_gpio.vvc_methods_pkg.all;
use bitvis_vip_gpio.gpio_bfm_pkg.all;
use bitvis_vip_gpio.td_vvc_framework_common_methods_pkg.all;
context bitvis_vip_gpio.vvc_context;
-- Test bench entity
entity tb_test is
end entity tb_test;
-- Test bench architecture
architecture func of tb_test is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant C_NR_LEDS: natural := 4;
begin
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and Executors
-----------------------------------------------------------------------------
i_test_harness : entity work.th_test
generic map(
NR_OF_LEDS => C_NR_LEDS
);
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
Then that’s probably why, I was testing with a newer version 2020.1
I see now with 10.5c that I get the same error as you.
I guess this was a Modelsim error that they have fixed so I suggest you use the workaround unless you want to use a newer version of Modelsim.