# \#uvvm **URL:** https://forum.uvvm.org/tag/uvvm/1.md [Latest](https://forum.uvvm.org/latest.md) · [Categories](https://forum.uvvm.org/categories.md) · [Tags](https://forum.uvvm.org/tags.md) --- ## [Is it possible to have an AXI LITE VVC as slave?](https://forum.uvvm.org/t/is-it-possible-to-have-an-axi-lite-vvc-as-slave/55)
**Author:** [@estudioFPGA](https://forum.uvvm.org/u/estudioFPGA)\ **Replies:** 3\ **Last updated:** [December 17, 2025, 1:06pm UTC](https://forum.uvvm.org/t/is-it-possible-to-have-an-axi-lite-vvc-as-slave/55 "2025-12-17T13:06:12Z")
Hello everyone, I have an entity whose interfaces are UART and AXI LITE Master. I managed to simulate the UART interfaces TX and RX with UVVM, but I am not able to set an AXI LITE VVC as slave connected to my Master int… --- ## [How to file a PR for a bug fix?](https://forum.uvvm.org/t/how-to-file-a-pr-for-a-bug-fix/505)
**Author:** [@MartinBoberTecmata](https://forum.uvvm.org/u/MartinBoberTecmata)\ **Replies:** 2\ **Last updated:** [November 20, 2025, 8:25am UTC](https://forum.uvvm.org/t/how-to-file-a-pr-for-a-bug-fix/505 "2025-11-20T08:25:13Z")
We have integrated UVVM tag 2024.10.08 into one of our projects and we recently found a bug that is still present on the current master branch. The fix is relatively simple (a one-liner) so I want to file a PR. Of cours… --- ## [GHDL and UVVM which releases](https://forum.uvvm.org/t/ghdl-and-uvvm-which-releases/468)
**Author:** [@adamt99](https://forum.uvvm.org/u/adamt99)\ **Replies:** 4\ **Last updated:** [January 25, 2025, 8:51am UTC](https://forum.uvvm.org/t/ghdl-and-uvvm-which-releases/468 "2025-01-25T08:51:19Z")
Hi I am creating some test benches for a client they want to use UVVM with GHDL. I grabbed the latest releases of both. But have some issues compiling the UART example design. How often is GHDL and UVVM tested are ther… --- ## [Imp port vs a tlm fifo in axi scoreboard in uvm](https://forum.uvvm.org/t/imp-port-vs-a-tlm-fifo-in-axi-scoreboard-in-uvm/463)
**Author:** [@kendu](https://forum.uvvm.org/u/kendu)\ **Replies:** 1\ **Last updated:** [January 2, 2025, 4:19pm UTC](https://forum.uvvm.org/t/imp-port-vs-a-tlm-fifo-in-axi-scoreboard-in-uvm/463 "2025-01-02T16:19:32Z")
I wanted to know if for AXI transactions can I just do with imp port in my Scoreboard which comes with a write method. Or is there a case where I will definitely need fifo in my Scoreboard for axi transactions.? The de… --- ## [UVVM vs OSVVM: The main benefits – and some history](https://forum.uvvm.org/t/uvvm-vs-osvvm-the-main-benefits-and-some-history/346)
**Author:** [@UVVM\_Team](https://forum.uvvm.org/u/UVVM_Team)\ **Replies:** 2\ **Last updated:** [June 21, 2024, 1:26pm UTC](https://forum.uvvm.org/t/uvvm-vs-osvvm-the-main-benefits-and-some-history/346 "2024-06-21T13:26:38Z")
As we (the UVVM team) have been asked several times about the differences between UVVM and OSVVM, and as we have seen lots of misleading “information” on this subject, we finally decided that it was about time to give … --- ## [AXI Verification Components, OSVVM vs UVVM](https://forum.uvvm.org/t/axi-verification-components-osvvm-vs-uvvm/435)
**Author:** [@okhajut](https://forum.uvvm.org/u/okhajut)\ **Replies:** 0\ **Last updated:** [May 10, 2024, 12:26am UTC](https://forum.uvvm.org/t/axi-verification-components-osvvm-vs-uvvm/435 "2024-05-10T00:26:13Z")
The UVVM provides the following VC for AXI: AXI4 Master/Slave, AXI4-Lite Master/Slave and AXI-Stream Source/Sink. Coincidently, OSVVM also provides VC for these busses. I have the following questions: Do the UVVM VC f… --- ## [How to send Avalon-ST packages with increasing channel signal within that package?](https://forum.uvvm.org/t/how-to-send-avalon-st-packages-with-increasing-channel-signal-within-that-package/426)
**Author:** [@Lymphater](https://forum.uvvm.org/u/Lymphater)\ **Replies:** 0\ **Last updated:** [March 6, 2024, 10:26am UTC](https://forum.uvvm.org/t/how-to-send-avalon-st-packages-with-increasing-channel-signal-within-that-package/426 "2024-03-06T10:26:12Z")
My Avalon-ST packages looks like this: \> SOP : \_\_| |\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_ \> CHx : \_\_|0|1|2|3|4|5|6|7|8|9|\_\_\_ \> DATA : \_\_ X X X X X X X X X X \_\_\_ \> VALID : \_\_|¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬|\_\_\_ \> EOP : \_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_| … --- ## [VVC generated file version-information request](https://forum.uvvm.org/t/vvc-generated-file-version-information-request/97)
**Author:** [@Eric](https://forum.uvvm.org/u/Eric)\ **Replies:** 2\ **Last updated:** [February 29, 2024, 1:53pm UTC](https://forum.uvvm.org/t/vvc-generated-file-version-information-request/97 "2024-02-29T13:53:23Z")
Hi, With the vvc\_generator.py you can generate VVC components. When generated, is there version information available as constants in the generated files? If not, can these be added? I would like to know the versio… --- ## [SPI BFM error run time in sample code](https://forum.uvvm.org/t/spi-bfm-error-run-time-in-sample-code/408)
**Author:** [@oruizd](https://forum.uvvm.org/u/oruizd)\ **Replies:** 3\ **Last updated:** [February 11, 2024, 7:10pm UTC](https://forum.uvvm.org/t/spi-bfm-error-run-time-in-sample-code/408 "2024-02-11T19:10:22Z")
Hi everyone, I’m working with SPI BFM on GHDL and I had a run time error with the UVVM\_SUPLEMETARY sample code (spi\_vvc\_tb.vhd): UVVM-master/bitvis\_vip\_scoreboard/src/generic\_sb\_pkg.vhd:546:14:error: type of variable “… --- ## [Collisions with Tready in Axi-Stream UVVM](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398)
**Author:** [@jose9ortiz](https://forum.uvvm.org/u/jose9ortiz)\ **Replies:** 3\ **Last updated:** [October 11, 2023, 5:40am UTC](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398 "2023-10-11T05:40:56Z")
Hello! I have a question about a conexion in Axi-Stream in BFM. I can’t get the Tready signal to work in the case of the slave. A data collision always appears in these signal. I know the problem is in the way that I h… --- ## [Library utils with "context" in Modelsim with UVVM-Master](https://forum.uvvm.org/t/library-utils-with-context-in-modelsim-with-uvvm-master/397)
**Author:** [@jose9ortiz](https://forum.uvvm.org/u/jose9ortiz)\ **Replies:** 3\ **Last updated:** [October 5, 2023, 8:40am UTC](https://forum.uvvm.org/t/library-utils-with-context-in-modelsim-with-uvvm-master/397 "2023-10-05T08:40:14Z")
Hello! I am having problems using UVVM-master in Modelsim, I have a project that I know it works in vivado and I wanted to try simulating it with UVVM-Master in Modelsim. the version of Modelsim DE-64 is 10.7 and the U… --- ## [Multiple I2C slave devices on the same lines](https://forum.uvvm.org/t/multiple-i2c-slave-devices-on-the-same-lines/345)
**Author:** [@zunderbird](https://forum.uvvm.org/u/zunderbird)\ **Replies:** 1\ **Last updated:** [April 24, 2023, 11:05am UTC](https://forum.uvvm.org/t/multiple-i2c-slave-devices-on-the-same-lines/345 "2023-04-24T11:05:19Z")
Hi In my hardware design, I have two i2c slave components connected to the same i2c lines, and I would like to simulate with the same architecture. I put 2 I2C\_VVC in my design, configured as slaves, connected to the s… --- ## [UVVM in Vivado / xsim](https://forum.uvvm.org/t/uvvm-in-vivado-xsim/365)
**Author:** [@Werterror](https://forum.uvvm.org/u/Werterror)\ **Replies:** 4\ **Last updated:** [April 21, 2023, 1:01pm UTC](https://forum.uvvm.org/t/uvvm-in-vivado-xsim/365 "2023-04-21T13:01:41Z")
Hi, is it possible to use UVVM with Vivado 2022.2? If so is there example of how to setup the environment like there is with UVM: UVM IN VIVADO Thank you in advance --- ## [Driving UVVM simulations using GNU make](https://forum.uvvm.org/t/driving-uvvm-simulations-using-gnu-make/316)
**Author:** [@amb5l](https://forum.uvvm.org/u/amb5l)\ **Replies:** 11\ **Last updated:** [January 17, 2023, 5:13pm UTC](https://forum.uvvm.org/t/driving-uvvm-simulations-using-gnu-make/316 "2023-01-17T17:13:19Z")
I’ve been experimenting with UVVM. I have managed to run the bitvis\_uart example from a makefile, using 3 different free simulators (GHDL, NVC and Questa Intel FPGA Edition). The makefile is quite simple: # simulation … --- ## [VVM for teaching verification at a UK university](https://forum.uvvm.org/t/vvm-for-teaching-verification-at-a-uk-university/341)
**Author:** [@MikeBartley](https://forum.uvvm.org/u/MikeBartley)\ **Replies:** 1\ **Last updated:** [October 31, 2022, 2:29pm UTC](https://forum.uvvm.org/t/vvm-for-teaching-verification-at-a-uk-university/341 "2022-10-31T14:29:59Z")
Hi All We are thinking of using UVVM for teaching verification at a UK university - do you know if there are some good open-source UVVM exercises or examples we can use for the students, please? Mike --- ## [Time out for uvvm cmd](https://forum.uvvm.org/t/time-out-for-uvvm-cmd/257)
**Author:** [@switise](https://forum.uvvm.org/u/switise)\ **Replies:** 7\ **Last updated:** [December 19, 2021, 1:36pm UTC](https://forum.uvvm.org/t/time-out-for-uvvm-cmd/257 "2021-12-19T13:36:42Z")
I m trying to verify my DUT that contaning a I2C master and i use I2C\_VCC as slave but i have this error Can you help me Thanks the error: The test sequencer: await\_uvvm\_initialization(VOID); start\_clock(CLOCK\_… --- ## [Disable all logging, only report when an error or failure occurs](https://forum.uvvm.org/t/disable-all-logging-only-report-when-an-error-or-failure-occurs/235)
**Author:** [@Eric](https://forum.uvvm.org/u/Eric)\ **Replies:** 2\ **Last updated:** [October 29, 2021, 10:45am UTC](https://forum.uvvm.org/t/disable-all-logging-only-report-when-an-error-or-failure-occurs/235 "2021-10-29T10:45:38Z")
Hi, How can I disable all text output or logging to the screen in UVVM? I tried disable\_log\_msg(ALL\_MESSAGES); But then still the ID\_BFM messages come printed. Is it possible to disable all logging? And I assume tha… --- ## [UVVM version v2 2021.10.22 is released](https://forum.uvvm.org/t/uvvm-version-v2-2021-10-22-is-released/232)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [October 22, 2021, 11:20am UTC](https://forum.uvvm.org/t/uvvm-version-v2-2021-10-22-is-released/232 "2021-10-22T11:20:10Z")
UVVM Functional Coverage and Advanced Randomisation is now released The ESA UVVM project has just published completely new UVVM functionality for Functional Coverage, Enhanced Randomisation and Optimised Randomisation. … --- ## [UVVM v2 2021.05.26 is released](https://forum.uvvm.org/t/uvvm-v2-2021-05-26-is-released/208)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 2\ **Last updated:** [September 29, 2021, 5:14am UTC](https://forum.uvvm.org/t/uvvm-v2-2021-05-26-is-released/208 "2021-09-29T05:14:04Z")
The release have the following changes: Corrected message ID for check\_value() methods in BFM packages. Added MATCH\_STD\_INCL\_Z to await\_value() for SL and SLV. Corrected timeout value parameter for await\_completion() i… --- ## [Issue with await\_value](https://forum.uvvm.org/t/issue-with-await-value/222)
**Author:** [@michael.campos](https://forum.uvvm.org/u/michael.campos)\ **Replies:** 7\ **Last updated:** [August 31, 2021, 7:28am UTC](https://forum.uvvm.org/t/issue-with-await-value/222 "2021-08-31T07:28:22Z")
Hi Marius, I am trying to add self checking mechanism to another module I am currently verifying. I am trying to implement an i2c\_slave\_receive in my tb. I can see the first data and clock transactions after 25 us, the… --- ## [The SPI\_VVCs GC\_DATA\_ARRAY\_WIDTH seemingly not determining the data array width](https://forum.uvvm.org/t/the-spi-vvcs-gc-data-array-width-seemingly-not-determining-the-data-array-width/129)
**Author:** [@Viljar](https://forum.uvvm.org/u/Viljar)\ **Replies:** 3\ **Last updated:** [August 26, 2021, 2:00pm UTC](https://forum.uvvm.org/t/the-spi-vvcs-gc-data-array-width-seemingly-not-determining-the-data-array-width/129 "2021-08-26T14:00:40Z")
Hi, I am working with the bitvis\_vip\_spi , and is trying to send more than 8 words (each 1 byte) with the spi\_master\_transmit\_and\_receive (or the transmit\_only variant). The GC\_DATA\_WIDTH and GC\_DATA\_ARRAY\_WIDTH have b… --- ## [Await\_value utils functionality issue](https://forum.uvvm.org/t/await-value-utils-functionality-issue/215)
**Author:** [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Replies:** 7\ **Last updated:** [July 9, 2021, 8:01am UTC](https://forum.uvvm.org/t/await-value-utils-functionality-issue/215 "2021-07-09T08:01:07Z")
Hi Marius, I am trying to add self checking mechanism to another module I am currently verifying. I currently have an issue when I use the following await\_value ie awaiting between 262000 ns & 270000 ns for state\_out v… --- ## [Potential bug with how the SPI\_VVC and SPI\_BFM interact to handel mulit-worded transmissions](https://forum.uvvm.org/t/potential-bug-with-how-the-spi-vvc-and-spi-bfm-interact-to-handel-mulit-worded-transmissions/119)
**Author:** [@Viljar](https://forum.uvvm.org/u/Viljar)\ **Replies:** 1\ **Last updated:** [June 8, 2021, 12:54pm UTC](https://forum.uvvm.org/t/potential-bug-with-how-the-spi-vvc-and-spi-bfm-interact-to-handel-mulit-worded-transmissions/119 "2021-06-08T12:54:22Z")
Something I find strange I found when using the bitvis\_vip\_spi: When handling multi-words (slv\_arrays) the spi\_bfm\_pkg uses a for loop that cycles 0 to \[data\]'length. When handling multi-words with the vvc the input ge… --- ## [Getting semaphore error when using parallel processes](https://forum.uvvm.org/t/getting-semaphore-error-when-using-parallel-processes/158)
**Author:** [@Hannu](https://forum.uvvm.org/u/Hannu)\ **Replies:** 10\ **Last updated:** [May 26, 2021, 1:24pm UTC](https://forum.uvvm.org/t/getting-semaphore-error-when-using-parallel-processes/158 "2021-05-26T13:24:05Z")
Hi We are running tests in multiple processes. DUT initialization is done in one process and then the tests are run in parallel processes. Register writes/reads are done through VVC methods in the parallel processes. Pr… --- ## [UVVM v2 2020.02.16 is out](https://forum.uvvm.org/t/uvvm-v2-2020-02-16-is-out/30)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [February 18, 2020, 1:46pm UTC](https://forum.uvvm.org/t/uvvm-v2-2020-02-16-is-out/30 "2020-02-18T13:46:40Z")
We have added som new features, fixed some bugs and added the following VIPs: Bitvis VIP Avalon Stream Bitvis VIP GMII Bitvis VIP RGMII --- ## [UVVM v2 2020.03.30 is released](https://forum.uvvm.org/t/uvvm-v2-2020-03-30-is-released/44)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [March 30, 2020, 1:36pm UTC](https://forum.uvvm.org/t/uvvm-v2-2020-03-30-is-released/44 "2020-03-30T13:36:27Z")
A new release of UVVM has been published : VVC Scoreboard improvements Simplified the checking methods Added requested report\_check\_counters() method Fixed bugs and added several other improvements Download a copy fro… --- ## [UVVM v2 2020.04.20 is release - with a new VIP](https://forum.uvvm.org/t/uvvm-v2-2020-04-20-is-release-with-a-new-vip/48)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [April 21, 2020, 7:02am UTC](https://forum.uvvm.org/t/uvvm-v2-2020-04-20-is-release-with-a-new-vip/48 "2020-04-21T07:02:31Z")
We have release a new version of UVVM: added selection of basic or advanced VVC when generating with vvc\_generator.py script added more section with transaction info usage to UVVM VVC Framework Essential Mechanisms pdf… --- ## [We have published beginner guides for UVVM and UVVM Light](https://forum.uvvm.org/t/we-have-published-beginner-guides-for-uvvm-and-uvvm-light/59)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [May 12, 2020, 11:49am UTC](https://forum.uvvm.org/t/we-have-published-beginner-guides-for-uvvm-and-uvvm-light/59 "2020-05-12T11:49:18Z")
The beginner guides will take you through the initial steps of getting started with UVVM / UVVM Light: UVVM guide PDF UVVM Light guide PDF --- ## [UVVM v2020.05.19 is out with lots of new stuff](https://forum.uvvm.org/t/uvvm-v2020-05-19-is-out-with-lots-of-new-stuff/61)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [May 19, 2020, 11:08am UTC](https://forum.uvvm.org/t/uvvm-v2020-05-19-is-out-with-lots-of-new-stuff/61 "2020-05-19T11:08:42Z")
We have updated UVVM and UVVM Light to version 2020.05.19 --- ## [UVVM v2020.06.23 is out](https://forum.uvvm.org/t/uvvm-v2020-06-23-is-out/72)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0\ **Last updated:** [June 24, 2020, 4:42am UTC](https://forum.uvvm.org/t/uvvm-v2020-06-23-is-out/72 "2020-06-24T04:42:14Z")
There is a new release out, v2020.06.23: Updated Ethernet and HVVC-to-VVC Bridge documentations Added Hierarchical VVCs section to UVVM Essential Mechanisms document Some bug fixes and other improvements. [Next page](https://forum.uvvm.org/tag/uvvm/1.md?match_all_tags=true&page=1&tags%5B%5D=uvvm)