# \#uvvm\_light

**URL:** https://forum.uvvm.org/tag/uvvm-light/12.md

[Latest](https://forum.uvvm.org/latest.md) · [Categories](https://forum.uvvm.org/categories.md) · [Tags](https://forum.uvvm.org/tags.md)

---

## [Axistream\_receive does not work](https://forum.uvvm.org/t/axistream-receive-does-not-work/380)

<div class="topic-metadata">

**Author:** [@Gabriel](https://forum.uvvm.org/u/Gabriel)\
**Replies:** 9\
**Last updated:** [August 10, 2023, 7:31am UTC](https://forum.uvvm.org/t/axistream-receive-does-not-work/380 "2023-08-10T07:31:15Z")

</div>

I’ve been coding a testbench for axistream with UVVM Light, my design file was done by using the AXI stream slave generated with Vivado, so I’m just making the testbench using UVVM. I can write data with axistream\_write(…

---

## [Issue with disabling logs for specific scope](https://forum.uvvm.org/t/issue-with-disabling-logs-for-specific-scope/336)

<div class="topic-metadata">

**Author:** [@akulinsk](https://forum.uvvm.org/u/akulinsk)\
**Replies:** 1\
**Last updated:** [October 28, 2022, 2:46pm UTC](https://forum.uvvm.org/t/issue-with-disabling-logs-for-specific-scope/336 "2022-10-28T14:46:31Z")

</div>

Hello! I am trying to disable ID\_POS\_ACK for one of the defined scopes, but the function disables all ID\_POS\_ACK logs. constant GEN\_SCOPE : string := "Generator"; constant CHECK\_SCOPE : string := "Checker"; begi…

---

## [Uvvm lite using block\_flag, unblock\_flag, await\_unblock\_flag and getting unexpected timeout](https://forum.uvvm.org/t/uvvm-lite-using-block-flag-unblock-flag-await-unblock-flag-and-getting-unexpected-timeout/163)

<div class="topic-metadata">

**Author:** [@bdecelles](https://forum.uvvm.org/u/bdecelles)\
**Replies:** 4\
**Last updated:** [April 12, 2021, 3:55pm UTC](https://forum.uvvm.org/t/uvvm-lite-using-block-flag-unblock-flag-await-unblock-flag-and-getting-unexpected-timeout/163 "2021-04-12T15:55:22Z")

</div>

I am using block\_flags for the fist time with UVVM Lite. I am getting a timeout that I do not expect. This is the stripped down code. I also have a signal global\_trigger : std\_logic :=‘Z’; Can you tell me what I am…
