# Wishbone write seems to go wrong

**URL:** <https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312>\
**Category:** Bitvis VIP Wishbone BETA\
**Created:** [August 18, 2022, 6:58am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312 "2022-08-18T06:58:18Z")\
**Posts on this page:** 10\
**Page:** 1

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [August 18, 2022, 6:58am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/1 "2022-08-18T06:58:18Z")

</div>

Hi,

I’m trying to get a Wishbone test bench setup working.  
I’m using a DUT like is shown on page 104 of this wishbone spec. See

> **[wbspec\_b4.pdf](https://cdn.opencores.org/downloads/wbspec_b4.pdf)**
>
> 1150.98 KB

The only difference is that I have a data path to 32 bits, and added an addr bus to it, although not used.

when I do wishbone write I get an error message.  
That error message occurs at the same sim time as all the execution is done.  
I don’t know what is causing this, as I assume the DUT in the specification is right.  
It can be my DUT, it also can be the VVC as it is in BETA

In my TB I have

```auto
...
wishbone_write (WISHBONE_VVCT, C_ID_WB_MASTER, v_addr, v_data, "a wishbone write");
await_completion ((WISHBONE_VVCT, C_ID_WB_MASTER, 5 * CLK_PERIOD);
...

```

In the QuestaSim simulation I get:

```auto
UVVM:	LOG_HDR 10000.0 ns TB seq. v_addr is 0xA5
UVVM:	LOG_HDR 10000.0 ns TB seq. v_data is 0xCAFEBABE
UVVM:	LOG_HDR 10000.0 ns WISHBONE_VVC, 10 ..Interpreter: Waiting for command 
UVVM:	LOG_HDR 10000.0 ns TB seq.(uvvm) ->wishbone_write ((WISHBONE_VVCT, 10,x"A5", x"CAFEBABE"): 'a wishbone write cycle'. [4]
UVVM:	LOG_HDR 10000.0 ns WISHBONE_VVC, 10 wishbone_write ((WISHBONE_VVCT, 10,x"A5", x"CAFEBABE"). Command received [4]
UVVM:	LOG_HDR 10000.0 ns WISHBONE_VVC, 10 wishbone_write ((WISHBONE_VVCT, 10,x"A5", x"CAFEBABE") - Will be executed [4]  	
UVVM:	LOG_HDR 10000.0 ns WISHBONE_VVC, 10 ..Interpreter: Waiting for command 
UVVM:
UVVM: ========================================================================================================================================
UVVM: ***TB_FAILURE #1***
UVVM: 10000 ns WISHBONE_VVC,10
UVVM: wishbone_write => Failed. Boolean was false. 'Sanity check: Check that the setup_time is more than 0 ns.'

```

Because I do a await\_completion of more then 0 ns I think I do it write.

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [August 18, 2022, 11:02am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/2 "2022-08-18T11:02:26Z")

</div>

It is apparently related to the first procedure lines of wishbone\_write in the wishbone\_bfm\_pkg:

```auto
procedure wishbone_write (
...
...
begin
    -- setup_time and hold_time checking
    check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
    check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
    check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
    check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);

```

This suggest that I first need to do something else.  
What is that?

Rgds,  
Eric

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [August 18, 2022, 11:37am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/3 "2022-08-18T11:37:43Z")

</div>

Apparently I need to change the C\_WISHBONE\_BFM\_CONFIG\_DEFAULT in the wishbone\_bfm\_pkg.vhd

By changing  
line 68  
`clock_period => 10 ns,` (was -1 ns)

line 71  
`setup_time => 2ns,` (was -1 ns)

line 72  
`hold_time => 2 ns,` (was -1 ns)

Simulation now completes.  
Why are these values on -1ns ?

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [August 19, 2022, 7:31am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/4 "2022-08-19T07:31:38Z")

</div>

Hi Eric,  
These values are set to -1 ns (i.e. an invalid value) so that the test designer is required to set them. Should you fail to set these values - and there were some valid, but incorrect, default values - you could run into problems with you testbench or even your testbench and DUT.

Br.  
Marius

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [August 19, 2022, 7:48am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/5 "2022-08-19T07:48:11Z")

</div>

I now got it working a bit further, I can do two writes, which goes back to back  
When I add some clocks to it then I get an error

```auto
wisbone_write (...)
await_completion (...)
wisbone_write (...)
await_completion (...)

Wait some clock periods
wisbone_write (...)
await_completion (...)

```

I now get the error:  
`await_value(std_logic, 0, 0 ns, 5ns) => Failed. Timed out after 5 ns. 'wishbone_write: timeout waiting for clk low_period for setup_time.'`

How can I fix this?  
I’m still using the values mentioned earlier in this thread (setup 2ns, hold 2ns, clock 10 ns)

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [August 23, 2022, 11:22am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/6 "2022-08-23T11:22:45Z")

</div>

Hi Marius,

Any idea on how to fix this? I’m running in circles at the moment.

Rgds.  
Eric

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [August 24, 2022, 6:32pm UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/7 "2022-08-24T18:32:40Z")

</div>

Hi Eric,  
It’s not clear to me why you get this timeout, but maybe you could share the transcript? Run with all log messages enabled.  
Why do yo have all those await\_completion() between the calls? Are you addressing different instances of the VVC? The commands are put inside a queue so if your goal is to have, say 3 wishbone\_write() before you want to do something else, just issue 3 wishbone\_write() VVC commands and then call the await\_completion(). See the uvvm\_vvc\_framework/doc/Common\_VVC\_Methods.pdf page 4 for details.

Br.  
Marius

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [August 25, 2022, 6:02am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/8 "2022-08-25T06:02:06Z")

</div>

About the await\_completion. I thought this was required. Apparently I miss understood.

Transcript of simulation:

```auto
# vsim -suppress 1083 work.tb_wb_slave_gpo 
# Start time: 07:58:38 on Aug 25,2022
# ** Note: (vsim-3812) Design is being optimized...
# // Questa Sim-64
# // Version 2021.1 win64 Jan 19 2021
# //
# // Copyright 1991-2021 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading uvvm_util.types_pkg(body)
# Loading uvvm_util.adaptations_pkg(body)
# Loading ieee.math_real(body)
# Loading uvvm_util.string_methods_pkg(body)
# Loading uvvm_util.protected_types_pkg(body)
# Loading uvvm_util.global_signals_and_shared_variables_pkg
# Loading uvvm_util.hierarchy_linked_list_pkg(body)
# Loading uvvm_util.license_pkg(body)
# Loading std.env(body)
# Loading uvvm_util.alert_hierarchy_pkg(body)
# Loading uvvm_util.methods_pkg(body)
# ** Note: 
# 
# 
# *****************************************************************************************************
# This is a ***LICENSED PRODUCT*** as given in the LICENSE.TXT in the root directory.
# *****************************************************************************************************
# 
# 
# Time: 0 ns Iteration: 0 Region: /methods_pkg File: ../../vendor_libs/uvvm/uvvm_util/script/../src/methods_pkg.vhd
# ** Note: 
# 
# =====================================================================================================
# =====================================================================================================
# This info section may be turned off via C_SHOW_UVVM_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd
# 
# Important Simulator setup: 
# - Set simulator to break on severity 'FAILURE' 
# - Set simulator transcript to a monospace font (e.g. Courier new)
# 
# UVVM Utility Library setup:
# - It is recommended to go through the two powerpoint presentations provided with the download
# - There is a Quick-Reference in the doc-directory
# - In order to change layout or behaviour - please check the src*/adaptations_pkg.vhd
# This is intended for personal or company customization
# 
# License conditions are given in LICENSE.TXT
# =====================================================================================================
# =====================================================================================================
# 
# 
# Time: 0 ns Iteration: 0 Region: /methods_pkg File: ../../vendor_libs/uvvm/uvvm_util/script/../src/methods_pkg.vhd
# Loading uvvm_util.bfm_common_pkg(body)
# Loading uvvm_util.generic_queue_pkg(body)
# Loading uvvm_util.rand_pkg(body)
# Loading uvvm_util.func_cov_pkg(body)
# Loading uvvm_vvc_framework.ti_protected_types_pkg(body)
# Loading uvvm_vvc_framework.ti_vvc_framework_support_pkg(body)
# Loading bitvis_vip_scoreboard.generic_sb_support_pkg(body)
# Loading bitvis_vip_wishbone.wishbone_bfm_pkg(body)
# Loading bitvis_vip_wishbone.vvc_cmd_pkg(body)
# Loading bitvis_vip_wishbone.td_target_support_pkg(body)
# Loading bitvis_vip_scoreboard.generic_sb_pkg(body)
# Loading bitvis_vip_wishbone.vvc_methods_pkg(body)
# Loading bitvis_vip_wishbone.td_vvc_framework_common_methods_pkg(body)
# Loading bitvis_vip_clock_generator.vvc_cmd_pkg(body)
# Loading bitvis_vip_clock_generator.td_target_support_pkg(body)
# Loading bitvis_vip_clock_generator.vvc_methods_pkg(body)
# Loading bitvis_vip_clock_generator.td_vvc_framework_common_methods_pkg(body)
# Loading bitvis_vip_spi.spi_bfm_pkg(body)
# Loading bitvis_vip_spi.transaction_pkg
# Loading bitvis_vip_spi.vvc_cmd_pkg(body)
# Loading bitvis_vip_spi.td_target_support_pkg(body)
# Loading bitvis_vip_spi.td_vvc_framework_common_methods_pkg(body)
# Loading bitvis_vip_spi.vvc_methods_pkg(body)
# Loading bitvis_vip_gpio.gpio_bfm_pkg(body)
# Loading bitvis_vip_gpio.transaction_pkg
# Loading bitvis_vip_gpio.vvc_cmd_pkg(body)
# Loading bitvis_vip_gpio.td_target_support_pkg(body)
# Loading bitvis_vip_gpio.vvc_methods_pkg(body)
# Loading bitvis_vip_gpio.td_vvc_framework_common_methods_pkg(body)
# Loading lib_cpld.cpld_constants_pkg(body)
# Loading lib_verification.verification_pkg(body)
# Loading work.tb_wb_slave_gpo(rtl)#1
# Loading bitvis_vip_clock_generator.td_cmd_queue_pkg
# Loading bitvis_vip_clock_generator.td_result_queue_pkg
# Loading bitvis_vip_clock_generator.td_vvc_entity_support_pkg(body)
# Loading bitvis_vip_wishbone.td_cmd_queue_pkg
# Loading bitvis_vip_wishbone.td_result_queue_pkg
# Loading bitvis_vip_wishbone.td_vvc_entity_support_pkg(body)
# Loading bitvis_vip_gpio.td_cmd_queue_pkg
# Loading bitvis_vip_gpio.td_result_queue_pkg
# Loading bitvis_vip_gpio.td_vvc_entity_support_pkg(body)
# Loading work.th_wb_slave_gpo(struct)#1
# Loading bitvis_vip_clock_generator.clock_generator_vvc(behave)#1
# UVVM: ID_CONSTRUCTOR 0.0 ns GPIO_VVC,31 VVC instantiated.
# UVVM: ID_CONSTRUCTOR_SUB 0.0 ns GPIO_VVC,31 Command queue instantiated and will give a warning when reaching 1000 elements in queue.
# UVVM: ID_CONSTRUCTOR_SUB 0.0 ns GPIO_VVC,31 Result queue instantiated and will give a warning when reaching 1000 elements in queue.
# UVVM: ID_CONSTRUCTOR 0.0 ns WISHBONE_VVC,14 VVC instantiated.
# UVVM: ID_CONSTRUCTOR_SUB 0.0 ns WISHBONE_VVC,14 Command queue instantiated and will give a warning when reaching 1000 elements in queue.
# UVVM: ID_CONSTRUCTOR_SUB 0.0 ns WISHBONE_VVC,14 Result queue instantiated and will give a warning when reaching 1000 elements in queue.
# UVVM: ID_CONSTRUCTOR 0.0 ns CLOCK_GENERATOR_VVC,0 VVC instantiated.
# UVVM: ID_CONSTRUCTOR_SUB 0.0 ns CLOCK_GENERATOR_VVC,0 Command queue instantiated and will give a warning when reaching 1000 elements in queue.
# UVVM: ID_CONSTRUCTOR_SUB 0.0 ns CLOCK_GENERATOR_VVC,0 Result queue instantiated and will give a warning when reaching 1000 elements in queue.
# UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns GPIO_VVC,31 ..Interpreter: Waiting for command
# UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns WISHBONE_VVC,14 ..Interpreter: Waiting for command
# UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns CLOCK_GENERATOR_VVC,0 ..Interpreter: Waiting for command
# UVVM: ID_CTRL 0.0 ns GPIO_VVC_SB,31 enable() => SB enabled. 'GPIO VVC SB Enabled'
# UVVM: ID_CTRL 0.0 ns GPIO_VVC_SB,31 config() => config applied to SB. 
# UVVM: ID_CTRL 0.0 ns GPIO_VVC_SB,31 enable_log_msg() => message id id_data enabled.
# UVVM: ID_CTRL 0.0 ns WISHBONE_VVC_SB,14 enable() => SB enabled. 'WISHBONE VVC SB Enabled'
# UVVM: ID_CTRL 0.0 ns WISHBONE_VVC_SB,14 config() => config applied to SB. 
# UVVM: ID_CTRL 0.0 ns WISHBONE_VVC_SB,14 enable_log_msg() => message id id_data enabled.
# UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns CLOCK_GENERATOR_VVC,0 ..Executor: Waiting for command
# UVVM:      
# UVVM: --------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: ***REPORT OF GLOBAL CTRL***
# UVVM: --------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: IGNORE STOP_LIMIT
# UVVM: NOTE : REGARD 0
# UVVM: TB_NOTE : REGARD 0
# UVVM: WARNING : REGARD 0
# UVVM: TB_WARNING : REGARD 0
# UVVM: MANUAL_CHECK : REGARD 0
# UVVM: ERROR : REGARD 1
# UVVM: TB_ERROR : REGARD 1
# UVVM: FAILURE : REGARD 1
# UVVM: TB_FAILURE : REGARD 1
# UVVM: --------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM:      
# UVVM:      
# UVVM: --------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: ***REPORT OF MSG ID PANEL***
# UVVM: --------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: ID Status
# UVVM: ------------------------ ------
# UVVM: ID_UTIL_BURIED : DISABLED
# UVVM: ID_BITVIS_DEBUG : DISABLED
# UVVM: ID_UTIL_SETUP : ENABLED
# UVVM: ID_LOG_MSG_CTRL : ENABLED
# UVVM: ID_ALERT_CTRL : ENABLED
# UVVM: ID_FINISH_OR_STOP : ENABLED
# UVVM: ID_CLOCK_GEN : ENABLED
# UVVM: ID_GEN_PULSE : ENABLED
# UVVM: ID_BLOCKING : ENABLED
# UVVM: ID_WATCHDOG : ENABLED
# UVVM: ID_RAND_GEN : DISABLED
# UVVM: ID_RAND_CONF : DISABLED
# UVVM: ID_FUNC_COV_BINS : DISABLED
# UVVM: ID_FUNC_COV_BINS_INFO : DISABLED
# UVVM: ID_FUNC_COV_RAND : DISABLED
# UVVM: ID_FUNC_COV_SAMPLE : DISABLED
# UVVM: ID_FUNC_COV_CONFIG : DISABLED
# UVVM: ID_POS_ACK : ENABLED
# UVVM: ID_LOG_HDR : ENABLED
# UVVM: ID_LOG_HDR_LARGE : ENABLED
# UVVM: ID_LOG_HDR_XL : ENABLED
# UVVM: ID_SEQUENCER : ENABLED
# UVVM: ID_SEQUENCER_SUB : ENABLED
# UVVM: ID_BFM : ENABLED
# UVVM: ID_BFM_WAIT : ENABLED
# UVVM: ID_BFM_POLL : ENABLED
# UVVM: ID_BFM_POLL_SUMMARY : ENABLED
# UVVM: ID_CHANNEL_BFM : ENABLED
# UVVM: ID_TERMINATE_CMD : ENABLED
# UVVM: ID_SEGMENT_INITIATE : ENABLED
# UVVM: ID_SEGMENT_COMPLETE : ENABLED
# UVVM: ID_SEGMENT_HDR : ENABLED
# UVVM: ID_SEGMENT_DATA : ENABLED
# UVVM: ID_PACKET_INITIATE : ENABLED
# UVVM: ID_PACKET_PREAMBLE : ENABLED
# UVVM: ID_PACKET_COMPLETE : ENABLED
# UVVM: ID_PACKET_HDR : ENABLED
# UVVM: ID_PACKET_DATA : ENABLED
# UVVM: ID_PACKET_CHECKSUM : ENABLED
# UVVM: ID_PACKET_GAP : ENABLED
# UVVM: ID_PACKET_PAYLOAD : ENABLED
# UVVM: ID_FRAME_INITIATE : ENABLED
# UVVM: ID_FRAME_COMPLETE : ENABLED
# UVVM: ID_FRAME_HDR : ENABLED
# UVVM: ID_FRAME_DATA : ENABLED
# UVVM: ID_COVERAGE_MAKEBIN : DISABLED
# UVVM: ID_COVERAGE_ADDBIN : DISABLED
# UVVM: ID_COVERAGE_ICOVER : DISABLED
# UVVM: ID_COVERAGE_CONFIG : ENABLED
# UVVM: ID_COVERAGE_SUMMARY : ENABLED
# UVVM: ID_COVERAGE_HOLES : ENABLED
# UVVM: ID_UVVM_SEND_CMD : ENABLED
# UVVM: ID_UVVM_CMD_ACK : ENABLED
# UVVM: ID_UVVM_CMD_RESULT : ENABLED
# UVVM: ID_CMD_INTERPRETER : ENABLED
# UVVM: ID_CMD_INTERPRETER_WAIT : ENABLED
# UVVM: ID_IMMEDIATE_CMD : ENABLED
# UVVM: ID_IMMEDIATE_CMD_WAIT : ENABLED
# UVVM: ID_CMD_EXECUTOR : ENABLED
# UVVM: ID_CMD_EXECUTOR_WAIT : ENABLED
# UVVM: ID_CHANNEL_EXECUTOR : ENABLED
# UVVM: ID_CHANNEL_EXECUTOR_WAIT : ENABLED
# UVVM: ID_NEW_HVVC_CMD_SEQ : ENABLED
# UVVM: ID_INSERTED_DELAY : ENABLED
# UVVM: ID_OLD_AWAIT_COMPLETION : ENABLED
# UVVM: ID_AWAIT_COMPLETION : ENABLED
# UVVM: ID_AWAIT_COMPLETION_LIST : ENABLED
# UVVM: ID_AWAIT_COMPLETION_WAIT : ENABLED
# UVVM: ID_AWAIT_COMPLETION_END : ENABLED
# UVVM: ID_UVVM_DATA_QUEUE : ENABLED
# UVVM: ID_CONSTRUCTOR : ENABLED
# UVVM: ID_CONSTRUCTOR_SUB : ENABLED
# UVVM: ID_VVC_ACTIVITY : ENABLED
# UVVM: ID_MONITOR : ENABLED
# UVVM: ID_MONITOR_ERROR : ENABLED
# UVVM: ID_DATA : ENABLED
# UVVM: ID_CTRL : ENABLED
# UVVM: ID_FILE_OPEN_CLOSE : ENABLED
# UVVM: ID_FILE_PARSER : ENABLED
# UVVM: ID_SPEC_COV : ENABLED
# UVVM: --------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM:      
# UVVM: ID_LOG_MSG_CTRL 0.0 ns TB seq. enable_log_msg(ALL_MESSAGES). 
# UVVM: ID_LOG_MSG_CTRL 0.0 ns TB seq. enable_log_msg(ID_LOG_HDR). 
# UVVM: ID_LOG_MSG_CTRL 0.0 ns TB seq. enable_log_msg(ID_SEQUENCER). 
# UVVM: ID_LOG_MSG_CTRL 0.0 ns TB seq. enable_log_msg(ID_UVVM_SEND_CMD). 
# UVVM: ID_UVVM_SEND_CMD 0.0 ns TB seq.(uvvm) ->start_clock(CLOCK_GENERATOR_VVC,0): 'Start CNV clock generator'. [1]
# UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns GPIO_VVC,31 ..Executor: Waiting for command
# UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns WISHBONE_VVC,14 ..Executor: Waiting for command
# UVVM: ID_CMD_INTERPRETER 0.0 ns CLOCK_GENERATOR_VVC,0 start_clock(CLOCK_GENERATOR_VVC,0). Command received [1]
# UVVM: ID_CMD_EXECUTOR 0.0 ns CLOCK_GENERATOR_VVC,0 start_clock(CLOCK_GENERATOR_VVC,0) - Will be executed [1]
# UVVM: ID_UVVM_CMD_ACK 0.0 ns TB seq.(uvvm) ACK received. [1]
# UVVM: ID_CLOCK_GEN 0.0 ns CLOCK_GENERATOR_VVC,0 Clock 'CNV_CLOCK' started
# UVVM: ID_CMD_INTERPRETER_WAIT 0.0 ns CLOCK_GENERATOR_VVC,0 ..Interpreter: Waiting for command
# UVVM: ID_CMD_EXECUTOR_WAIT 0.0 ns CLOCK_GENERATOR_VVC,0 ..Executor: Waiting for command
# UVVM: 
# UVVM: 
# UVVM: ID_LOG_HDR 10000.0 ns TB seq. Configure WB VVC 
# UVVM: -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: ID_UVVM_SEND_CMD 10000.0 ns TB seq.(uvvm) ->enable_log_msg(WISHBONE_VVC,14, ID_BFM): . [2]
# UVVM: ID_CMD_INTERPRETER 10000.0 ns WISHBONE_VVC,14 enable_log_msg(WISHBONE_VVC,14, ID_BFM). Command received [2]
# UVVM: ID_LOG_MSG_CTRL 10000.0 ns WISHBONE_VVC,14 enable_log_msg(ID_BFM). ' [2]'
# UVVM: ID_UVVM_CMD_ACK 10000.0 ns TB seq.(uvvm) ACK received. [2]
# UVVM: ID_CMD_INTERPRETER_WAIT 10000.0 ns WISHBONE_VVC,14 ..Interpreter: Waiting for command
# UVVM: ID_UVVM_SEND_CMD 10000.0 ns TB seq.(uvvm) ->enable_log_msg(WISHBONE_VVC,14, ID_FINISH_OR_STOP): . [3]
# UVVM: ID_CMD_INTERPRETER 10000.0 ns WISHBONE_VVC,14 enable_log_msg(WISHBONE_VVC,14, ID_FINISH_OR_STOP). Command received [3]
# UVVM: ID_LOG_MSG_CTRL 10000.0 ns WISHBONE_VVC,14 enable_log_msg(ID_FINISH_OR_STOP). ' [3]'
# UVVM: ID_UVVM_CMD_ACK 10000.0 ns TB seq.(uvvm) ACK received. [3]
# UVVM: 
# UVVM: 
# UVVM: ID_LOG_HDR 10000.0 ns TB seq. Starting simulation of TB for WB_SLAVE using VVCs
# UVVM: -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: 
# UVVM: 
# UVVM: ID_LOG_HDR 10000.0 ns TB seq. WB write, read and check example
# UVVM: -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# UVVM: ID_CMD_INTERPRETER_WAIT 10000.0 ns WISHBONE_VVC,14 ..Interpreter: Waiting for command
# UVVM: ID_UVVM_SEND_CMD 10000.0 ns TB seq.(uvvm) ->wishbone_write(WISHBONE_VVC,14, x"A5", x"CAFEBABE"): 'a wishbone write cycle'. [4]
# UVVM: ID_CMD_INTERPRETER 10000.0 ns WISHBONE_VVC,14 wishbone_write(WISHBONE_VVC,14, x"A5", x"CAFEBABE"). Command received [4]
# UVVM: ID_CMD_EXECUTOR 10000.0 ns WISHBONE_VVC,14 wishbone_write(WISHBONE_VVC,14, x"A5", x"CAFEBABE") - Will be executed [4]
# UVVM: ID_UVVM_CMD_ACK 10000.0 ns TB seq.(uvvm) ACK received. [4]
# UVVM: ID_CMD_INTERPRETER_WAIT 10000.0 ns WISHBONE_VVC,14 ..Interpreter: Waiting for command
# UVVM: ID_AWAIT_COMPLETION 10000.0 ns TB seq.(uvvm) await_completion(WISHBONE_VVC,14, 20000 ns): . [5]
# UVVM: ID_AWAIT_COMPLETION_WAIT 10000.0 ns TB seq.(uvvm) ..await_completion(WISHBONE_VVC,14, 20000 ns) - Pending completion. [5]
# UVVM: ID_BFM 11002.0 ns WISHBONE_VVC,14 wishbone_write(A:x"A5", x"CAFEBABE") completed. 'a wishbone write cycle' [4]
# UVVM: ID_AWAIT_COMPLETION_END 11002.0 ns TB seq.(uvvm) await_completion(WISHBONE_VVC,14, 20000 ns)=> WISHBONE_VVC,14 finished. [5]
# UVVM: ID_UVVM_SEND_CMD 11002.0 ns TB seq.(uvvm) ->wishbone_write(WISHBONE_VVC,14, x"A5", x"FACEB00C"): 'a wishbone write cycle'. [6]
# UVVM: ID_CMD_EXECUTOR_WAIT 11002.0 ns WISHBONE_VVC,14 ..Executor: Waiting for command
# UVVM: ID_CMD_INTERPRETER 11002.0 ns WISHBONE_VVC,14 wishbone_write(WISHBONE_VVC,14, x"A5", x"FACEB00C"). Command received [6]
# UVVM: ID_CMD_EXECUTOR 11002.0 ns WISHBONE_VVC,14 wishbone_write(WISHBONE_VVC,14, x"A5", x"FACEB00C") - Will be executed [6]
# UVVM: ID_UVVM_CMD_ACK 11002.0 ns TB seq.(uvvm) ACK received. [6]
# UVVM: ID_CMD_INTERPRETER_WAIT 11002.0 ns WISHBONE_VVC,14 ..Interpreter: Waiting for command
# UVVM: ID_AWAIT_COMPLETION 11002.0 ns TB seq.(uvvm) await_completion(WISHBONE_VVC,14, 20000 ns): . [7]
# UVVM: ID_AWAIT_COMPLETION_WAIT 11002.0 ns TB seq.(uvvm) ..await_completion(WISHBONE_VVC,14, 20000 ns) - Pending completion. [7]
# UVVM: ID_BFM 12002.0 ns WISHBONE_VVC,14 wishbone_write(A:x"A5", x"FACEB00C") completed. 'a wishbone write cycle' [6]
# UVVM: ID_AWAIT_COMPLETION_END 12002.0 ns TB seq.(uvvm) await_completion(WISHBONE_VVC,14, 20000 ns)=> WISHBONE_VVC,14 finished. [7]
# UVVM: ID_CMD_EXECUTOR_WAIT 12002.0 ns WISHBONE_VVC,14 ..Executor: Waiting for command
# UVVM: ID_UVVM_SEND_CMD 15012.0 ns TB seq.(uvvm) ->wishbone_write(WISHBONE_VVC,14, x"A5", x"FACEB00C"): 'a wishbone write cycle'. [8]
# UVVM: ID_CMD_INTERPRETER 15012.0 ns WISHBONE_VVC,14 wishbone_write(WISHBONE_VVC,14, x"A5", x"FACEB00C"). Command received [8]
# UVVM: ID_CMD_EXECUTOR 15012.0 ns WISHBONE_VVC,14 wishbone_write(WISHBONE_VVC,14, x"A5", x"FACEB00C") - Will be executed [8]
# UVVM: ID_UVVM_CMD_ACK 15012.0 ns TB seq.(uvvm) ACK received. [8]
# UVVM: ID_CMD_INTERPRETER_WAIT 15012.0 ns WISHBONE_VVC,14 ..Interpreter: Waiting for command
# UVVM: ID_AWAIT_COMPLETION 15012.0 ns TB seq.(uvvm) await_completion(WISHBONE_VVC,14, 20000 ns): . [9]
# UVVM: ID_AWAIT_COMPLETION_WAIT 15012.0 ns TB seq.(uvvm) ..await_completion(WISHBONE_VVC,14, 20000 ns) - Pending completion. [9]
# UVVM: 
# UVVM: =========================================================================================================================================================================
# UVVM: ***TB_FAILURE #1***
# UVVM: 15017 ns TB seq.
# UVVM: await_value(std_logic 0, 0 ns, 5 ns) => Failed. Timed out after 5 ns. 'wishbone_write: timeout waiting for clk low period for setup_time.'
# UVVM: 
# UVVM: Simulator has been paused as requested after 1 TB_FAILURE
# UVVM: ***To find the root cause of this alert, step out the HDL calling stack in your simulator.***
# UVVM: ***For example, step out until you reach the call from the test sequencer.***
# UVVM: =========================================================================================================================================================================
# UVVM: 
# UVVM: 
# ** Note: stop
# Time: 15017 ns Iteration: 0 Instance: /tb_wb_slave_gpo/i_test_harness/i_wb_master_vvc
# Break in Subprogram alert at ../../vendor_libs/uvvm/uvvm_util/script/../src/methods_pkg.vhd line 3702
# End time: 07:58:45 on Aug 25,2022, Elapsed time: 0:00:07
# Errors: 0, Warnings: 0, Suppressed Warnings: 4
[sim_all.bat] An error occured!
[sim_all.bat] ----- END -----

```

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [August 25, 2022, 6:33am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/9 "2022-08-25T06:33:36Z")

</div>

Hi,  
The BFM is complaining that your clock is not running (or it’s running to slow). Is your clock generator running and is its clock period matching the wishbone configured clock period, setup and hold times?

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [October 3, 2022, 8:43am UTC](https://forum.uvvm.org/t/wishbone-write-seems-to-go-wrong/312/10 "2022-10-03T08:43:01Z")

</div>

Hi Marius,

I finally have the time to get back on this.  
Your right, the clock seems to be too slow.  
I get the test bench working when I use a clock period in the range of 6 ns - 33 ns.  
Bigger or lower will produce an error.

Wishbone is a new interface to me, and I was not aware that there was a clock constrain of a min /max period value on Wishbone.

So your reply fix my issue.

Rgds,  
Eric