# Welcome to Discourse

**URL:** <https://forum.uvvm.org/t/welcome-to-discourse/7>\
**Category:** Uncategorized\
**Created:** [January 7, 2020, 12:24pm UTC](https://forum.uvvm.org/t/welcome-to-discourse/7 "2020-01-07T12:24:43Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![system](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/9a19954730a4b5e4ad804f4a04da840c935e9349.png) [@system](https://forum.uvvm.org/u/system)\
**Post date:** [January 7, 2020, 12:24pm UTC](https://forum.uvvm.org/t/welcome-to-discourse/7/1 "2020-01-07T12:24:43Z")

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This is a forum for UVVM users to discuss questions, challenges and best practices for UVVM based FPGA and ASIC VHDL verification.