# VVC Pipelined and out of order transactions

**URL:** <https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489>\
**Category:** VVC Framework\
**Created:** [April 10, 2025, 12:57pm UTC](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489 "2025-04-10T12:57:30Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![AlexK](https://avatars.discourse-cdn.com/v4/letter/a/91b2a8/32.png) [@AlexK](https://forum.uvvm.org/u/AlexK)\
**Post date:** [April 10, 2025, 12:57pm UTC](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489/1 "2025-04-10T12:57:30Z")

</div>

Hallo,  
how do I tell to my testbench to pipeline the transcations with a single command ? Currently I use the await\_completion(…) command after every axi\_write or axi\_read. Is there a way to tell the VVC to always carry out pipelined transactions?  
Thanks!!

---

<div class="post-metadata">

**Author:** ![EspenTa](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/espenta/32/52_2.png) [@EspenTa](https://forum.uvvm.org/u/EspenTa)\
**Post date:** [April 15, 2025, 5:17pm UTC](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489/2 "2025-04-15T17:17:00Z")

</div>

Hi,  
The VVC will always carry out pipelined commands as soon as possible. I.e. as soon as something makes time pass. This could be an await\_completion() as you mentioned, but could also be a normal VHDL wait statement, or any other time consuming command.  
There is currently no single command available to do say an axi\_write() automatically followed by an await\_completion().  
You could of course make your own overload or dedicated procedures to do exactly that.  
If however, this is something that is generally wanted by the UVVM community, this could be evaluated as an extension to UVVM itself.