# Verification for simple parallel bus with data valid

**URL:** <https://forum.uvvm.org/t/verification-for-simple-parallel-bus-with-data-valid/437>\
**Category:** General questions\
**Created:** [May 15, 2024, 6:31pm UTC](https://forum.uvvm.org/t/verification-for-simple-parallel-bus-with-data-valid/437 "2024-05-15T18:31:13Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![aghoras](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/aghoras/32/148_2.png) [@aghoras](https://forum.uvvm.org/u/aghoras)\
**Post date:** [May 15, 2024, 6:31pm UTC](https://forum.uvvm.org/t/verification-for-simple-parallel-bus-with-data-valid/437/1 "2024-05-15T18:31:13Z")

</div>

Hello,  
I’m using UVVM to verify a DUT that has a simple data output bus which consists of 16 parallel bits and a data valid bit. What is the right UVVM module I can use to queue up checks for the expected values coming out of my DUT?

Thanks

---

<div class="post-metadata">

**Author:** ![UVVM\_Team](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/uvvm_team/32/102_2.png) [@UVVM\_Team](https://forum.uvvm.org/u/UVVM_Team)\
**Post date:** [June 21, 2024, 2:10pm UTC](https://forum.uvvm.org/t/verification-for-simple-parallel-bus-with-data-valid/437/2 "2024-06-21T14:10:13Z")

</div>

Hi,  
Currently your best choice would be to use AXI-stream or Avalon-stream.  
Note however, that the signal records for these protocols in UVVM contain the complete set of protocol signals. You thus need to connect up ‘data’ and ‘valid’ and set the rest to “passive” values (i.e. set record element ‘tready’ fixed to ‘1’ in your TB).  
I guess we could evaluate making a simpler BFM and VVC for this purpose, but that is not top priority just now. Do you only have single word accesses?

---

<div class="post-metadata">

**Author:** ![aghoras](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/aghoras/32/148_2.png) [@aghoras](https://forum.uvvm.org/u/aghoras)\
**Post date:** [August 1, 2024, 2:40pm UTC](https://forum.uvvm.org/t/verification-for-simple-parallel-bus-with-data-valid/437/3 "2024-08-01T14:40:27Z")

</div>

Yes. I just need to read one word at a time. I ended up making my own simple interface using the GPIO BFM and a bunch of procedure calls. I didn’t feel like making my own VVC.

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [September 29, 2024, 8:54am UTC](https://forum.uvvm.org/t/verification-for-simple-parallel-bus-with-data-valid/437/4 "2024-09-29T08:54:55Z")

</div>

Good to hear you found a solution.  
Note that you can use the vvc\_generator.py script to develop your own VVC and BFM.