# UVVM VVC of a simple counter (having issues getting it to simulate with counter\_vvc in place) **URL:** \ **Category:** VVC Framework\ **Created:** [May 26, 2021, 2:19pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209 "2021-05-26T14:19:19Z")\ **Posts on this page:** 20\ **Page:** 1
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [May 26, 2021, 2:19pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/1 "2021-05-26T14:19:19Z")
Hi, I am new to the UVVM VVC creation. I am trying to convert my current verification platform to using VVC. I generated the templates by executing the python vvc\_generator.py for my counter DUT. Looked at the following link which has a simple counter and tried to follow same approach like they do to build the UVVM platform with VVC in place ``` https://www.edaplayground.com/x/2LhW ``` This simple counter design.vhd, testbench is not complete ie test sequencer process is missing calling the procedural commands etc I am using a different counter as my DUT to this one just incrementing and reseting. Used gen\_pulse within my testbench to create an active high pulse for the reset. This works ok. Reset connects directly to the DUT (counter) within the test harness (ie it is not part of my counter\_vvc). This reset pulse works fine. Instantiated also within my testbech the bitvis clock\_generator\_vvc. This works fine too. I created a BFM procedure counter\_count\_up and placed this within the counter\_bfm\_pkg I called this counter\_count\_up procedure within my testbench Test Sequencer process and the counting up works fine right after reset (this is without the VVC framework in place). The counter\_count\_up procedure just generates an active high enable signal (out) and counts up. It also does self checking of the counter at various points using the check\_value uvvm utils procedure. Simulated this without the counter\_vvc first in place and that was ok. **However, having problems at the moment when I added the BFM procedure call in the counter\_vvc within the VVC dedicated operations**. case v\_cmd.operation COUNT\_UP was used for this and within vvc\_cmd\_pkg.vhd I included COUNT\_UP within the t\_operation type list. The clk is visible but the counter\_vvc counter interface ‘in\_enable’ and ‘out\_counter’ interface signals do not perform as expected. The template counter\_vvc.vhd included a constructor, command interpreter, command executor and command termination handler. It is my understanding that the only things I need to add in this template file is to Insert BFM procedure calls within the case v\_cmd.operation and update the top-level port of the counter\_vvc to insert BFM interface signals. Isn’t this the case? Do I need to create a Config initializer process (like the clock\_generator\_vvc does)? I also noticed that the vvc\_methods\_pkg.vhd examples VVC procedure declarations inserted in this file just include example the following: – \ Please insert the VVC procedure declarations here procedure counter\_cnt\_up ( signal VVCT : inout t\_vvc\_target\_record; constant vvc\_instance\_idx : in integer; constant cycles : in natural; constant msg : in string ); ie it includes VVCT signal and not the original interface signals. Is this correct? Can someone explain here this matter too. Within the package body of vcc\_methods\_pkg included the following which included the COUNT\_UP: procedure counter\_count\_up( signal VVCT : inout t\_vvc\_target\_record; constant vvc\_instance\_idx : in integer; constant cycles : in natural; constant msg : in string ) is use std.textio.side; constant proc\_name : string := “counter\_count\_up”; constant proc\_call : string := proc\_name & “(” & to\_string(VVCT, vvc\_instance\_idx) – First part common for all & ", " & integer’image(cycles) & “)”; begin set\_general\_target\_and\_command\_fields (VVCT, vvc\_instance\_idx, proc\_call, msg, QUEUED, COUNT\_UP); shared\_vvc\_cmd.cycles := cycles; send\_command\_to\_vvc(VVCT); end procedure; * * * **The main issue I have is that the ‘in\_enable’ is low at the beginning as expected BUT as soon as this signal tries to go to ‘1’ from the counter\_count\_up BFM procedure after executing the following command within the testbench:** **counter\_count\_up(0, “Enable the counter to start counting up”, in\_clock, in\_enable, out\_counter, C\_SCOPE);**\*\* **the in\_enable line is ‘X’ and stays 'X’** Initially had my in\_enable signal declared as input port at the test harness level but had the following compilation error: "Cannot assign to object ‘in\_enable’ of mode IN Changed it then top level test harness in\_enable from input to output port. Then after running the simulation it shown this ‘X’ propagation issue on the ‘in\_enable’ when the above command was executed from the testbench (test sequencer process). in\_enable is input to the DUT (counter). Test harness also instantiates the counter\_vvc module and connected there the clock, reset, in\_enable & out\_counter. This is URGENT. Prompt reply to this matter will be appreciated Regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [May 27, 2021, 8:27am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/2 "2021-05-27T08:27:56Z")
> [@KevNug](#): > > v\_cmd.operation Hi Kevin, I’ve just had a short test using the VVC in your testbench and the counter seems to work (only showing the code I’ve added to your testbench): ``` log(ID_SEQUENCER, "Resetting counter", C_SCOPE); counter_reset(COUNTER_VVCT, 1, "Reset counter value"); await_completion(COUNTER_VVCT, 1, 2*C_CLK_PERIOD, "Await execution"); -- verify counter value counter_check(COUNTER_VVCT, 1, x"00", "Checking counter reset value"); log(ID_SEQUENCER, "Loading counter value x01", C_SCOPE); counter_load(COUNTER_VVCT, 1, x"01", "Loading counter value x01"); await_completion(COUNTER_VVCT, 1, 2*C_CLK_PERIOD, "Await execution"); -- verify counter value counter_check(COUNTER_VVCT, 1, x"01", "Checking counter value"); log(ID_SEQUENCER, "Counting up 5 clock periods", C_SCOPE); counter_count_up(COUNTER_VVCT, 1, 5, "Counting up 5 cycles"); await_completion(COUNTER_VVCT, 1, 5*C_CLK_PERIOD, "Await execution"); -- verify counter value counter_check(COUNTER_VVCT, 1, x"06", "Checking counter value"); log(ID_SEQUENCER, "Simulation finished", C_SCOPE); -- done wait for C_CLK_PERIOD; ----------------------------------------------------------------------------- -- Ending the simulation ----------------------------------------------------------------------------- ``` This is how the wave view looks like ![Skjermbilde 2021-05-27 kl. 10.27.15](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/ec852b5ca0ec4cd1588ac5838b5d6a8725468946.png) Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [May 27, 2021, 7:21pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/3 "2021-05-27T19:21:16Z")
Hi Marius, The key to my VVC issue was that I was trying to call in my Testbench the BFM procedure of counter\_count\_up and not the VVC related one (VVC one uses paramerers such as eg COUNTER\_VVCT set within it etc). Your short test of commands gave me this clue (understanding). Managed to get my counter going. I was using the check\_value uvvm\_utils procedure checking out my counter values. Could create my own counter\_check one which could check a bigger range of values in one go. I could see also the [UVVM Counter Testbench Example - EDA Playground](https://www.edaplayground.com/x/2LhW) counter example now working. My counter as mentioned in my previous message is different than this one. Kind regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [May 28, 2021, 4:56am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/4 "2021-05-28T04:56:52Z")
Great, You should be able to call the BFM procedures from the testbench sequencer as well. The sequencer code will have to be changed obviously, as the BFM procedures will block/stall the sequencer while the procedure is being executed. Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [May 28, 2021, 3:02pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/5 "2021-05-28T15:02:23Z")
Hi Marius, For the VVC platform I have ie included VVC procedure declarations & implementations within the vvc\_methods\_pkg.vhd the implementation (ie wiggling of the counter DUT signals) is done in my counter\_bfm\_pkg.vhd package body part. Currently, within my counter\_vvc.vhd v\_cmd.operation state machine I inserted the BFM procedure calls for eg COUNT\_UP case included the counter\_count\_up (ie this calls the corresponding procedure counter\_count\_up in the BFM package counter\_bfm\_pkg.vhd). Is this expected here? VVC procedures framework looks to interact with the BFM procedures to acquire info about the DUT interface signals wiggling. Is this the case? Can this interface wiggling signals be done at the VVC procedures level without requiring the BFM procedures? or is it easier to do it this way ie develop first BFM procedures and then re-use them within the VVC framework structure. Your comments on this matter will be appreciated. Regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [May 28, 2021, 5:58pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/6 "2021-05-28T17:58:39Z")
Hi, The pin wiggle should be done by the BFM, and when you have a VVC, it will be responsible for calling the BFM procedure. This way your test sequencer is free to perform several tasks in parallell, e.g. call another VVC to perform some other work, or maybe do some logging, checking etc. Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [May 28, 2021, 6:13pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/7 "2021-05-28T18:13:59Z")
Great. Thanks. This is how I implemented it and I will leave it like this. This was a question asked by one of my colleagues today when I presented my UVVM VVC testcase to them ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [May 31, 2021, 5:15pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/8 "2021-05-31T17:15:28Z")
Hi Marius, Another question. We will like to incorporate PASS/FAIL reporting into the UVVM platform scripts. I have initially included within my testbench ‘check\_value’ UVVM utils procedure to check the counter at various points. eg check\_value(x"0002", out\_counter(1), TB\_ERROR, “Checking out\_counter(1) value5”, C\_SCOPE); If the accepted (ie expected) value is x"0002" and the captured out\_counter(1) value at that point is x"0002" then within simulation/modelsim directory currently see \_Alert.txt file empty. However, if a TB\_ERROR is detected then it will report it within the \_Alert.txt. We will also like to be able to report the following info into eg a log file using UVVM command features (if possible). Will be looking to add this feature too into my scripts. Any initial thoughts wrt existing UVVM commands that can achieve this will be appreciated. module name procedure name accepted value captured value Result Counter check\_value ? x"0002" x"0002" PASS Counter check\_value ? x"0003" x"0002" FAIL ::: * * * Wrt the extended UVVM features for the generated VVC, I did not enable these options yet as reported previously: - Enable scoreboard - Activity watchdog & transaction info Kind regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 1, 2021, 9:15am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/9 "2021-06-01T09:15:45Z")
Hi, You could use the checker functions, e.g. variable v\_check\_ok : boolean; … v\_check\_ok := check\_value(…); if v\_check\_ok = False then … See section 1.1 in the Utility Library Quick Reference for various checker implementations. Note that you can change the number of expected (TB\_)ERROR, (TB\_)WARNING etc, and also set the stop limit - e.g. set\_alert\_stop\_limit(TB\_WARNING, 2); – stop sim after 2 TB\_WARNING (see section 1.3 in the Utility Library QR) And you can use the report function - report\_alert\_counters(FINAL); - which will present the number of alerts detected vs expected, and report a simulation PASS/FAIL based on this (see final line in the report): ![Skjermbilde 2021-06-01 kl. 11.15.07](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/f48de7cb125d52cbbd9b7a2b7c2bb1f7090b6408.png) Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 1, 2021, 1:26pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/10 "2021-06-01T13:26:48Z")
Hi Marius, Thanks. Haven’t used v\_check\_ok variable yet because I noticed that the simulation as soon as it finds 1 error it stops immediately reporting where the error was and does not continue until the end of the simulation where I can report pass/fail on each of the check\_value commands used within the testbench. I then added the following at the top of the p\_main testbench process: increment\_expected\_alerts\_and\_stop\_limit(TB\_ERROR,3,“Expecting 3 more TB\_ERRORS”); Is this the Alert handling function you meant to suggest? This allowed the tool to carry on and complete the whole simulation process reporting all the alert results at the end. In this example I introduced 1 TB\_ERROR to one of the check\_value calls. Tried also the following: increment\_expected\_alerts\_and\_stop\_limit(TB\_ERROR,0,“Expecting 0 or more TB\_ERRORS”); After compiling the testbench, it did not report any testbench compilation warnings here, so 0 looks to be a valid parameter too (and it stopped the simulation as soon as 1 TB\_ERROR was found). Ideally, we will like to catch all TB\_ERRORS in the testbench and report at the end all PASSes & FAILs. Can we eg disable the expected alert TB\_ERROR stop limit ? In the example above, used a value of 3 within the increment\_expected\_alerts\_and\_stop\_limit() but if there are eg 3 recorded in this example, the simulation will stop. Like to avoid using a large number eg 100 and keep changing it to a bigger value, if it reaches it ie 100 or more TB\_ERRORs … Kind regards, Kevin ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 1, 2021, 2:45pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/11 "2021-06-01T14:45:33Z")
Hi Marius, I managed to disable the expected alert TB\_ERROR stop limit by using the following command instead of the increment\_expected\_alerts\_and\_stop\_limit() one : ``` set_alert_stop_limit(TB_ERROR, 0); -- 0 means never stop ``` * * * Will like if I start using the v\_check\_ok variable as you suggested to then dump the PASS/FAIL results in an output file with a certain reporting structure (similar to what TEXTIO Write does) Regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 1, 2021, 5:52pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/12 "2021-06-01T17:52:10Z")
Hi Kevin, Yes, you can disable the alert to allow for the TB to run through all the simulations without stopping. Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 2, 2021, 9:12am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/13 "2021-06-02T09:12:20Z")
Hi Marius, To write to a log file the correct structure we will like, I added WRITE TXT IO instructions as shown in the example below right after each v\_check\_ok := check\_value(xxx) statement. I also included opening an “out.txt” in WRITE\_MODE at the top of the testbench and a loop (looping once) at the beginning writing the top header part (not shown the whole code below). eg WRITE(L, string’(“Sim time: Module’s name: Procedure name: Accepted value: Captured value: Result”)); I have also used: report\_alert\_counters(FINAL) and this displays a final summary of all Alerts but this is displayed in the uvvm format not the format we will like (but I included this as well at the end of the testbench to report this too - useful to have). Any comments here too will be appreciated. Testbench got much bigger in size by adding the individual WRITE procedure commands right after each v\_check\_ok := check\_value(xxxx) Ffi see my example below. If I can move each block of the WRITE procedure commands to 1 procedure call this could shorten the procedure calls added into my testbench or use any other single uvvm procedural calls replacing the WRITE ones I used that would be great. Looking into this matter too but if you have any comments on this matter please let me know. eg ::: v\_check\_ok := check\_value(x"0099", out\_counter(0), TB\_ERROR, “Checking out\_counter(0) value4”, C\_SCOPE); WRITE(L, NOW, left, 15); WRITE(L, string’(“Counter”), right, 17); WRITE(L, string’(“check\_value”), right, 17); WRITE(L, string’(“0x0099”), right, 16); WRITE(L, string’(“0x”) & to\_hstring(out\_counter(0)), right, 21); if v\_check\_ok = false then WRITE(L, string’(“FAIL”), right, 19); WRITELINE(F, L); ErrCnt \<= ErrCnt + 1; else WRITE(L, string’(“PASS”), right, 19); WRITELINE(F, L); TotalPass \<= TotalPass + 1; end if; TotalCnt \<= TotalCnt + 1; wait until rising\_edge(in\_clock); ::: Regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 2, 2021, 10:58am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/14 "2021-06-02T10:58:23Z")
Hi Kevin, Keeping the summary report is fine I think. It would definitely be an improvement to the testbench sequencer readability if you put the check, counter updates and all of the write commands in a dedicated procedure that is called from the sequencer. Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 2, 2021, 4:17pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/15 "2021-06-02T16:17:46Z")
Hi Marius, Wondering whether the counter updates and the WRITE commands can be done with uvvm util procedures than having to create mine (time consuming) using eg the ‘log’ procedure to display the main header string and any other ready made uvvm procedures to display the text numeric results within the right columns including PASS/FAIL. Your reply to this matter will be appreciated. Regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 2, 2021, 6:05pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/16 "2021-06-02T18:05:22Z")
Hi, You can use the util procedures, but you should create a procedure/function that calls them and not make changes in the procedures. See section 1.2 about logging in the Utility Library QR. E.g ``` -- TB locally declared function (or put in a package) function check_and_log( constant exp_value : std_logic_vector; constant act_value : std_logic_vector) return boolean is variable v_check_ok : boolean; begin v_check_ok := check_value(exp_value, act_value, TB_ERROR, "checking DUT output", C_SCOPE); if v_check_ok = false then log(....... FAIL); else log(......PASS); end if; return v_check_ok; end function check_and_log; -- select log file in the start of the sequencer set_log_file_name("counter_checker_log.txt"); ... -- call function from inside loop in the sequencer v_ok := check_and_log(exp_value, act_value); if v_ok = false then err_cnt := err_cnt + 1; end if; -- pass_cnt = tot_cnt - err_cnt ``` Something like this. Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 2, 2021, 9:42pm UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/17 "2021-06-02T21:42:43Z")
Hi Marius, Thanks for your suggestion. If I use the check\_value within the function check\_and\_log (this function was placed in a package), I get the following warning: # \*\* Warning: (vcom-1285) Cannot call impure function “check\_value” from pure function “check\_and\_log”. Does the check\_and\_log need to be a procedure instead of a function? Kind regards, Kevin ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 3, 2021, 6:00am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/18 "2021-06-03T06:00:42Z")
Hi, Just make it an impure function. Br, Marius ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 3, 2021, 11:28am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/19 "2021-06-03T11:28:45Z")
Hi Marius, That’s what I thought too afterwards :-). Made it as an impure function and it worked ok. Thanks. I have now a counter\_check\_log.txt file reporting the the UVVM commands: eg UVVM: ID\_SEQUENCER … UVVM: ID\_CMD\_INTERPRETER\_WAIT … UVVM: ID\_CMD\_EXECUTOR\_WAIT … UVVM: ID\_CMD\_INTERPRETER … UVVM: ID\_CMD\_EXECUTOR … :: UVVM: ID\_SEQUENCER 11300.0 ns CLOCKCYCLECOUNTER BFM Module’s name: ClockCycleCounter | Procedure name: check\_value UVVM: ID\_SEQUENCER 11300.0 ns CLOCKCYCLECOUNTER BFM Accepted value: 00000000000001100011 | Captured value: 0000000001100011 | Result PASS UVVM: ID\_SEQUENCER 11400.0 ns CLOCKCYCLECOUNTER BFM Module’s name: ClockCycleCounter | Procedure name: check\_value UVVM: ID\_SEQUENCER 11400.0 ns CLOCKCYCLECOUNTER BFM Accepted value: 0000000000000000 | Captured value: 0000000000000000 | Result PASS :: UVVM: ID\_SEQUENCER 6573100.0 ns CLOCKCYCLECOUNTER BFM Module’s name: ClockCycleCounter | Procedure name: check\_value UVVM: ID\_SEQUENCER 6573100.0 ns CLOCKCYCLECOUNTER BFM Accepted value: 0000000000000010 | Captured value: 0000000000000001 | Result FAIL ::: UVVM: ID\_SEQUENCER 6573200.0 ns TB seq. Summary- | Total test = 10 | Total pass = 9 | Total fail = 1 * * * Within the testbench I specifically instructed it to do the following: disable\_log\_msg(ALL\_MESSAGES); enable\_log\_msg(ID\_SEQUENCER); but it displayed within the counter\_checker\_log.txt all the other commands too. Will like to filter everything out and just log the following: UVVM: ID\_SEQUENCER xxx CLOCKCYCLECOUNTER BFM xxx + UVVM: ID\_SEQUENCER xxx TB seq. xxx just the last summary report which shows the Total PASS/FAIL. Looking to use PowerShell to do this at the moment but if you have any other suggestions eg using specific UVVM instructions to do it please let me know. Kind regards, Kevin ---
**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Post date:** [June 4, 2021, 1:08am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209/20 "2021-06-04T01:08:59Z")
Hi Marius, Used PowerShell and got it to report what I wanted. But found a better way to do it using the ‘log’ procedure. Managed to get it reporting to a .txt file the lines I want by incorporating within the ‘log’ procedure extra parameters such as “MyScope”, shared\_msg\_id\_panel, LOG\_ONLY, “counter\_checker\_myscope\_log.txt”, append\_mode Kind regards, Kevin [Next page](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209.md?page=2)