# Take the Aldec FPGA verification Survey

**URL:** <https://forum.uvvm.org/t/take-the-aldec-fpga-verification-survey/343>\
**Category:** Announcements\
**Created:** [November 1, 2022, 3:45pm UTC](https://forum.uvvm.org/t/take-the-aldec-fpga-verification-survey/343 "2022-11-01T15:45:39Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![UVVM\_Team](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/uvvm_team/32/102_2.png) [@UVVM\_Team](https://forum.uvvm.org/u/UVVM_Team)\
**Post date:** [November 1, 2022, 3:45pm UTC](https://forum.uvvm.org/t/take-the-aldec-fpga-verification-survey/343/1 "2022-11-01T15:45:39Z")

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Take the survey below to show which HDL you are using (e.g. VHDL) and which verification methodology you are using (e.g. UVVM).  
[https://resources.aldec.com/acton/form/23474/00d8:d-0001/0/-/-/-/-/index.htm](https://resources.aldec.com/acton/form/23474/00d8:d-0001/0/-/-/-/-/index.htm)