# Problem with axilite writing by using VVC

**URL:** <https://forum.uvvm.org/t/problem-with-axilite-writing-by-using-vvc/384>\
**Category:** Bitvis VIP AXI-Lite\
**Tags:** question\
**Created:** [August 14, 2023, 10:53am UTC](https://forum.uvvm.org/t/problem-with-axilite-writing-by-using-vvc/384 "2023-08-14T10:53:25Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![Jacinto](https://avatars.discourse-cdn.com/v4/letter/j/6bbea6/32.png) [@Jacinto](https://forum.uvvm.org/u/Jacinto)\
**Post date:** [August 14, 2023, 10:53am UTC](https://forum.uvvm.org/t/problem-with-axilite-writing-by-using-vvc/384/1 "2023-08-14T10:53:25Z")

</div>

Hi everyone.  
I’m trying to make a simple testbench for AXI Lite but the following error appears: timeout for uvvm cmd, while waiting for acknowledge vvc, I read in this forum that it could be solved by increasing the completition time with await\_completition() function but it hasn’t worked for me, I appreciate your help.  
My code is the following:

library IEEE;  
use IEEE.Std\_logic\_1164.all;  
use IEEE.Numeric\_Std.all;  
library uvvm\_util;  
context uvvm\_util.uvvm\_util\_context;  
library uvvm\_vvc\_framework;  
use uvvm\_vvc\_framework.ti\_vvc\_framework\_support\_pkg.all;  
library bitvis\_vip\_axilite;  
context bitvis\_vip\_axilite.vvc\_context;

entity axilitevvc\_indra\_tb is  
end;

architecture bench of axilitevvc\_indra\_tb is

component axilitevvc\_indra  
generic (  
C\_S\_AXI\_DATA\_WIDTH : integer := 32;  
C\_S\_AXI\_ADDR\_WIDTH : integer := 4  
);  
port (  
S\_AXI\_ACLK : in std\_logic;  
S\_AXI\_ARESETN : in std\_logic;  
S\_AXI\_AWADDR : in std\_logic\_vector(C\_S\_AXI\_ADDR\_WIDTH-1 downto 0);  
S\_AXI\_AWPROT : in std\_logic\_vector(2 downto 0);  
S\_AXI\_AWVALID : in std\_logic;  
S\_AXI\_AWREADY : out std\_logic;  
S\_AXI\_WDATA : in std\_logic\_vector(C\_S\_AXI\_DATA\_WIDTH-1 downto 0);  
S\_AXI\_WSTRB : in std\_logic\_vector((C\_S\_AXI\_DATA\_WIDTH/8)-1 downto 0);  
S\_AXI\_WVALID : in std\_logic;  
S\_AXI\_WREADY : out std\_logic;  
S\_AXI\_BRESP : out std\_logic\_vector(1 downto 0);  
S\_AXI\_BVALID : out std\_logic;  
S\_AXI\_BREADY : in std\_logic;  
S\_AXI\_ARADDR : in std\_logic\_vector(C\_S\_AXI\_ADDR\_WIDTH-1 downto 0);  
S\_AXI\_ARPROT : in std\_logic\_vector(2 downto 0);  
S\_AXI\_ARVALID : in std\_logic;  
S\_AXI\_ARREADY : out std\_logic;  
S\_AXI\_RDATA : out std\_logic\_vector(C\_S\_AXI\_DATA\_WIDTH-1 downto 0);  
S\_AXI\_RRESP : out std\_logic\_vector(1 downto 0);  
S\_AXI\_RVALID : out std\_logic;  
S\_AXI\_RREADY : in std\_logic  
);  
end component;

constant C\_S\_AXI\_DATA\_WIDTH : integer := 32;  
constant C\_S\_AXI\_ADDR\_WIDTH : integer := 4;  
constant C\_CLK\_PERIOD : time:= 10 ns;  
signal clock\_ena : boolean := true;  
signal S\_AXI\_ACLK : std\_logic;  
signal S\_AXI\_ARESETN : std\_logic;  
signal S\_AXI\_AWADDR : std\_logic\_vector(C\_S\_AXI\_ADDR\_WIDTH-1 downto 0);  
signal S\_AXI\_AWPROT : std\_logic\_vector(2 downto 0);  
signal S\_AXI\_AWVALID : std\_logic;  
signal S\_AXI\_AWREADY : std\_logic;  
signal S\_AXI\_WDATA : std\_logic\_vector(C\_S\_AXI\_DATA\_WIDTH-1 downto 0);  
signal S\_AXI\_WSTRB : std\_logic\_vector((C\_S\_AXI\_DATA\_WIDTH/8)-1 downto 0);  
signal S\_AXI\_WVALID : std\_logic;  
signal S\_AXI\_WREADY : std\_logic;  
signal S\_AXI\_BRESP : std\_logic\_vector(1 downto 0);  
signal S\_AXI\_BVALID : std\_logic;  
signal S\_AXI\_BREADY : std\_logic;  
signal S\_AXI\_ARADDR : std\_logic\_vector(C\_S\_AXI\_ADDR\_WIDTH-1 downto 0);  
signal S\_AXI\_ARPROT : std\_logic\_vector(2 downto 0);  
signal S\_AXI\_ARVALID : std\_logic;  
signal S\_AXI\_ARREADY : std\_logic;  
signal S\_AXI\_RDATA : std\_logic\_vector(C\_S\_AXI\_DATA\_WIDTH-1 downto 0);  
signal S\_AXI\_RRESP : std\_logic\_vector(1 downto 0);  
signal S\_AXI\_RVALID : std\_logic;  
signal S\_AXI\_RREADY : std\_logic ;  
signal axilite\_if: t\_axilite\_if  
(  
write\_address\_channel(  
awaddr(C\_S\_AXI\_ADDR\_WIDTH-1 downto 0)  
),  
write\_data\_channel(  
wdata(C\_S\_AXI\_DATA\_WIDTH-1 downto 0),  
wstrb(4-1 downto 0)  
),  
read\_address\_channel(  
araddr(C\_S\_AXI\_ADDR\_WIDTH-1 downto 0)  
),  
read\_data\_channel(  
rdata(C\_S\_AXI\_DATA\_WIDTH-1 downto 0)  
)  
);  
begin

uut: axilitevvc\_indra generic map ( C\_S\_AXI\_DATA\_WIDTH =\> C\_S\_AXI\_DATA\_WIDTH,  
C\_S\_AXI\_ADDR\_WIDTH =\> C\_S\_AXI\_ADDR\_WIDTH )  
port map ( S\_AXI\_ACLK =\> S\_AXI\_ACLK,  
S\_AXI\_ARESETN =\> S\_AXI\_ARESETN,  
S\_AXI\_AWADDR =\> axilite\_if.write\_address\_channel.awaddr,  
S\_AXI\_AWPROT =\> axilite\_if.write\_address\_channel.awprot,  
S\_AXI\_AWVALID =\> axilite\_if.write\_address\_channel.awvalid,  
S\_AXI\_AWREADY =\> axilite\_if.write\_address\_channel.awready,  
S\_AXI\_WDATA =\> axilite\_if.write\_data\_channel.wdata,  
S\_AXI\_WSTRB =\> axilite\_if.write\_data\_channel.wstrb,  
S\_AXI\_WVALID =\> axilite\_if.write\_data\_channel.wvalid,  
S\_AXI\_WREADY =\> axilite\_if.write\_data\_channel.wready,  
S\_AXI\_BRESP =\> axilite\_if.write\_response\_channel.bresp,  
S\_AXI\_BVALID =\> axilite\_if.write\_response\_channel.bvalid,  
S\_AXI\_BREADY =\> axilite\_if.write\_response\_channel.bready,  
S\_AXI\_ARADDR =\> axilite\_if.read\_address\_channel.araddr,  
S\_AXI\_ARPROT =\> axilite\_if.write\_address\_channel.awprot,  
S\_AXI\_ARVALID =\> axilite\_if.read\_address\_channel.arvalid,  
S\_AXI\_ARREADY =\> axilite\_if.read\_address\_channel.arready,  
S\_AXI\_RDATA =\> axilite\_if.read\_data\_channel.rdata,  
S\_AXI\_RRESP =\> axilite\_if.read\_data\_channel.rresp,  
S\_AXI\_RVALID =\> axilite\_if.read\_data\_channel.rvalid,  
S\_AXI\_RREADY =\> axilite\_if.read\_data\_channel.rready );

i\_ti\_uvvm\_engine : entity uvvm\_vvc\_framework.ti\_uvvm\_engine;  
clock\_generator(S\_AXI\_ACLK, clock\_ena, C\_CLK\_PERIOD, “AXI Lite Clock Signal”);  
gen\_pulse(S\_AXI\_ARESETN,‘0’, 2\*C\_CLK\_PERIOD, “AXI Lite Reset Signal”);

p\_axiliteVVC:  
process

begin

```
axilite_if <= init_axilite_if_signals(C_S_AXI_ADDR_WIDTH,C_S_AXI_DATA_WIDTH);
shared_axilite_vvc_config(1).bfm_config.clock_period := C_CLK_PERIOD;

```

wait\_until\_given\_time\_after\_rising\_edge(S\_AXI\_ACLK,3\*C\_CLK\_PERIOD);

```
log("WRITING BY USING VCC FOR AXILITE");

axilite_write(AXILITE_VVCT, 1, x"F", x"00000054", "Written data");

await_completion(AXILITE_VVCT, 1, 1000 ns);

wait;

```

end process;

end;

 ![image](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/21959ba5ca4f3bcfcda2145fad26cc50558b6437.png)

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [August 16, 2023, 7:17am UTC](https://forum.uvvm.org/t/problem-with-axilite-writing-by-using-vvc/384/2 "2023-08-16T07:17:38Z")

</div>

Hi,  
Where do instantiate the VVC?

Br  
Marius

---

<div class="post-metadata">

**Author:** ![Jacinto](https://avatars.discourse-cdn.com/v4/letter/j/6bbea6/32.png) [@Jacinto](https://forum.uvvm.org/u/Jacinto)\
**Post date:** [August 16, 2023, 7:21am UTC](https://forum.uvvm.org/t/problem-with-axilite-writing-by-using-vvc/384/3 "2023-08-16T07:21:54Z")

</div>

Hi Marius.  
I didn’t know that I’ve got to do so, can you give an example of it ?  
The only thing that I’ve instantiated is the following:  
` i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;`  
I’m not completely sure if I’m using the whole set of needed libraries for axilite VVC.

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [August 16, 2023, 9:49am UTC](https://forum.uvvm.org/t/problem-with-axilite-writing-by-using-vvc/384/4 "2023-08-16T09:49:03Z")

</div>

The VVC is an entity, so you need to instantiate it as you would with any other entity.  
That would be something like this:

```auto
  axilite_vvc : entity bitvis_vip_axilite.axilite_vvc
    generic map(
      GC_ADDR_WIDTH => C_ADDR_WIDTH,
      GC_DATA_WIDTH => C_DATA_WIDTH,
      GC_INSTANCE_IDX => C_AXILITE_VVC_IDX
    )
    port map(
      clk => clk,
      axilite_vvc_master_if => axilite_if
    );

```

where `C_AXILITE_VVC_IDX` is a constant for the instance number for your VVC, e.g. 1. And you use the same number/constant when calling the VVC methods and other methods that interacts with the VVC - such as `await_completion()`. C\_ADDR\_WIDTH and C\_DATA\_WIDTH are other constants that you need to define. You can have a look at the documentation for this in the [VVC QR](https://github.com/UVVM/UVVM/blob/master/bitvis_vip_axilite/doc/axilite_vvc_QuickRef.pdf) - page 2.

Your code will then use this number/constant:

```auto
axilite_write(AXILITE_VVCT, C_AXILITE_VVC_IDX, x"F", x"00000054", "Written data");
await_completion(AXILITE_VVCT, C_AXILITE_VVC_IDX, 1000 ns);

```

Br,  
Marius