# No feasible entries error

**URL:** <https://forum.uvvm.org/t/no-feasible-entries-error/308>\
**Category:** General questions\
**Created:** [August 4, 2022, 12:30pm UTC](https://forum.uvvm.org/t/no-feasible-entries-error/308 "2022-08-04T12:30:59Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![Naveed](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/naveed/32/99_2.png) [@Naveed](https://forum.uvvm.org/u/Naveed)\
**Post date:** [August 4, 2022, 12:30pm UTC](https://forum.uvvm.org/t/no-feasible-entries-error/308/1 "2022-08-04T12:30:59Z")

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Hi,

Apologies in advance if this is too naive or basic question since I am learning UVVM and encountering problems and Google is unable to help.

I am setting an enable signal in the TB using gpio\_bfm\_pkg using following command (tried both)

```auto
gpio_set(en,"Setting enable to 1",1);

```

```auto
gpio_set(en,"Setting enable to 1",'1');

```

where `en` is defined as `std_logic` but I get error complaining

(vcom-1600) No feasible entries for subprogram “gpio\_set”.

I think this corresponds to that I am not using the command in correct way but apparently I don’t see any problem. Maybe gpio\_set expects vector but I dont want to give it a vector input even though it is a single bit. Anyone has some better suggestions?

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**Author:** ![EspenTa](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/espenta/32/52_2.png) [@EspenTa](https://forum.uvvm.org/u/EspenTa)\
**Post date:** [August 4, 2022, 2:54pm UTC](https://forum.uvvm.org/t/no-feasible-entries-error/308/2 "2022-08-04T14:54:00Z")

</div>

Hi,

gpio\_set() is only defined for std\_logic\_vector and not for std\_logic.  
[UVVM/gpio\_bfm\_pkg.vhd at master · UVVM/UVVM · GitHub](https://github.com/UVVM/UVVM/blob/master/bitvis_vip_gpio/src/gpio_bfm_pkg.vhd) line 62.  
There is no overload for std\_logic, so you need to convert/cast/change to std\_logic\_vector.

– Espen

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<div class="post-metadata">

**Author:** ![Naveed](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/naveed/32/99_2.png) [@Naveed](https://forum.uvvm.org/u/Naveed)\
**Post date:** [August 5, 2022, 7:39am UTC](https://forum.uvvm.org/t/no-feasible-entries-error/308/3 "2022-08-05T07:39:42Z")

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Thank you Espen for the reply,

Actually I thought the same workaround but I didn’t think it’d be a good workaround as it might cause some unknown problems since the signal was used at multiple places in different ways.

And since it is someone else’s code, I would not like to change its structure by typecasting multiple logical signals in the code.

Is it possible to create my own bfm that supports std\_logic? Is there any ref doc for that?

N

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**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [August 5, 2022, 9:01am UTC](https://forum.uvvm.org/t/no-feasible-entries-error/308/4 "2022-08-05T09:01:15Z")

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Hi,  
You can create your own BFM, but it would be much easier to just create a wrapper procedure that takes a std\_logic and converts it to std\_logic\_vector and calls the gpio\_set/get() BFM procedure inside your testbench .

Br.  
Marius