# Multiple VVCs question (1 testbench, 1 test harness, 1 test sequencer process?)

**URL:** <https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212>\
**Category:** VVC Framework\
**Created:** [June 4, 2021, 2:35pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212 "2021-06-04T14:35:14Z")\
**Posts on this page:** 13\
**Page:** 2

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**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [June 15, 2021, 6:03pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/21 "2021-06-15T18:03:12Z")

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Hi Kevin,  
For a setup with 1 testbench, multiple test harnesses, I guess you can create a test\_lib and compile both adc\_vvc\_th.vhd and i2c\_vvc\_th.vhd to this library, along with testbench.vhd. From the testbench perspective you will reference the test-harnesses by work.\<interface\_name\>\_vvc\_th

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 15, 2021, 7:12pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/22 "2021-06-15T19:12:20Z")

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Hi Marius,

Thanks for your reply to the 4 extra td\_ files matter. I compiled this earlier for the ClockCycleCounter one wrt 4 td\_ files so all 10 files were compiled to the bitvis\_vip\_clockcyclecounter library and simulation results were still successful. This was my testcase with just 1 DUT and 1 Test Harness.

> > You can see the compile order in e.g. bitvis\_vip\_sbi/doc/sbi\_vvc\_qr.pdf - final page.

I can see from that final .pdf page that the vvc\_context.vhd was missing from the list (only 9 files are listed there. They should be 10). I included that in my compilation list as the last one to be compiled.

Kind regards,  
Kevin

---

<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 15, 2021, 7:32pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/23 "2021-06-15T19:32:57Z")

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Hi Marius,

Another thing I noticed. One of the files VVC generator generated automatically was the vvc\_context.vhd file. Recall that I had to replace within it:

–use bitvis\_vip\_clockcyclecounter.clockcyclecounter\_bfm\_pkg.t\_clockcyclecounter\_if;  
–use bitvis\_vip\_clockcyclecounter.clockcyclecounter\_bfm\_pkg.t\_clockcyclecounter\_bfm\_config;  
–use bitvis\_vip\_clockcyclecounter.clockcyclecounter\_bfm\_pkg.C\_CLOCKCYCLECOUNTER\_BFM\_CONFIG\_DEFAULT;

with:

use bitvis\_vip\_clockcyclecounter.clockcyclecounter\_bfm\_pkg.all;

otherwise had a compilation error:

# \*\* Error: ../vvc\_vhdl/vvc\_tb.vhd(187): (vcom-1136) Unknown identifier “counter\_check” when compiling my testbench.

counter\_check is a procedure I created within the clockcyclecounter\_bfm\_pkg.vhd

Why did it list individually the 3 above separate ones (the ones I commented out above)? These could be all replaced by:

```
 use bitvis_vip_clockcyclecounter.clockcyclecounter_bfm_pkg.all;

```

Any other suggestions or do you agree with my change?  
Please comment here.

Regards,  
Kevin

---

<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 16, 2021, 9:30am UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/24 "2021-06-16T09:30:59Z")

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> [@Marius](#):
>
> For a setup with 1 testbench, multiple test harnesses, I guess you can create a test\_lib and compile both adc\_vvc\_th.vhd and i2c\_vvc\_th.vhd to this library, along with testbench.vhd. From the testbench perspective you will reference the test-harnesses by work.\<interface\_name\>\_vvc\_th

Hi Marius,

Wrt my setup with 1 testbench, multiple test harnesses (eg 2 test harnesses so far), I created test\_lib and tried to compile both test harnesses (adc\_vvc\_th.vhd and i2c\_vvc\_th.vhd) to this library.

It started now reporting many compilation errors eg

\*\* Error: (vcom-11) Could not find work.common.

# \*\* Error (suppressible): ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(22): (vcom-1195) Cannot find expanded name “work.Common”.

# \*\* Error: ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(22): Unknown expanded name.

I compiled this within my .do file script already before hand as follows:  
vcom -2008 -work work {../../vhdl\_code/Common.vhd}

but it flagged it again as an Error (see above).

* * *

The common.vhd is a package vhd file we use which declares all the types, subtypes, constants etc for our main FPGA. The DUTs were using eg the type ‘Words’ declaration and they were picking this up from this package. Used this type within my test harness port map declaration and defined this at the top as:  
use work.Common.all;

## The ClockCycleCounter DUT was also using it and declared it also at the top as: use work.Common.all; (DUT should remain as it is without any changes)

I tried to compile the Common.vhd within the work library just before compiling the test harness but it flagged the same error as above again.

I then added the following in **bold** within my .do file just before compiling the test harness:  
**vcom -2008 -work test\_lib {../../vhdl\_code/Common.vhd}**

vcom -2008 -work test\_lib {../vvc\_vhdl/adc/adc\_vvc\_th.vhd}

it started then flagging Errors with the rest of the hierarchy:

# \*\* Error: (vcom-11) Could not find work.clockcyclecounter.

# \*\* Error (suppressible): ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(66): (vcom-1195) Cannot find expanded name “work.ClockCycleCounter”.

# \*\* Error: ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(66): Unknown expanded name.

After I added the following in **bold** too ie

vcom -2008 -work test\_lib {../../vhdl\_code/Common.vhd}  
**vcom -2008 -work test\_lib {../../vhdl\_code/timer/ClockCycleCounter.vhd}**

vcom -2008 -work test\_lib {../vvc\_vhdl/adc/adc\_vvc\_th.vhd}

it flagged the following error:

# \*\* Error: (vcom-11) Could not find work.clockcyclecounter\_vvc.

# \*\* Error (suppressible): ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(91): (vcom-1195) Cannot find expanded name “work.clockcyclecounter\_vvc”.

# \*\* Error: ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(91): Unknown expanded name.

etc..

Do I have to re-compile all the submodules into test\_lib including the VVCs etc? I was not expecting this here. I must be doing something wrong..

* * *

Before I had the test harness and testbench compiled within work library but had issues when it was compiling the testbench. Changed the ‘work’ library to ‘test\_lib’ as you suggested but it started flagging the above errors when it was trying to compile the 1st test harness.

Within my test harness eg adc\_vvc\_th.vhd, I currently declare in the instantiation part of the DUT and VVC as follows:

i\_ClockCycleCounter: entity work.ClockCycleCounter  
::

i\_clockcyclecounter\_vvc: entity work.clockcyclecounter\_vvc  
::

–

I also tried to change within the adc\_vvc\_th.vhd to the following for the VVC instance:

i\_clockcyclecounter\_vvc: entity bitvis\_vip\_clockcyclecounter.clockcyclecounter\_vvc  
::

but had other compilation errors such as:

\*\* Error: ../vvc\_vhdl/adc/adc\_vvc\_th.vhd(103): Signal [mode OUT port] “out\_counter” is type work.Common.Words; expecting type bitvis\_vip\_clockcyclecounter.Common.Words.

Will appreciate your comments to this matter.

Regards,  
Kevin

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<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 16, 2021, 1:20pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/25 "2021-06-16T13:20:59Z")

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Hi Marius,

Wrt above email I reported earlier “setup with 1 testbench, multiple test harnesses (eg 2 test harnesses so far)” wrt errors seen, I think I resolved all of them.

I compiled the clockcyclecounter DUT into a separate library adc\_lib  
and the bfm, vvc packages and adc\_vvc\_th.vhd added:

library adc\_lib;  
use adc\_lib.Common.all;

The compilation flow went through ok.

The other test harness DUT was compiled within i2c\_lib and referenced within the test harness instantiation part as  
i\_checkStable: entity i2c\_lib.checkStable  
:::

I created also a test\_lib and compiled both adc\_vvc\_th.vhd and i2c\_vvc\_th.vhd to this library, along with testbench.vhd (as you suggested).

Test harness instances within the testbench I referenced both test harnesses with ‘work.\<interface\_name\>\_vvc\_th’ as you suggested in your previous email.

Testbench compiled ok too.

Declared at the top of the testbench also:  
library adc\_lib;  
use adc\_lib.Common.all;

because it was using within it in the 1st test harness instance one of the Common package declarations.

I had an error kickstarting simulation but this is something else which I will rectify too shortly.

Hope the simulation with 1 testbench and 2 test harnesses runs ok. Will report results soon.

Best regards,  
Kevin

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<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 16, 2021, 2:52pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/26 "2021-06-16T14:52:44Z")

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Hi Marius,

Managed to get the combined 1 testbench, 2 test harnesses to simulate ok 🙂

Moved the ti\_uvvm\_engine instance to the testbench level and removed it from the test harnesses because had the following warning:  
“ti\_uvvm\_engine seems to have been instantiated more than once in this testbench system”

Best regards,  
Kevin

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [June 17, 2021, 7:07am UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/27 "2021-06-17T07:07:11Z")

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Hi Kevin,  
Great! Yes, the ti\_uvvm\_engine should only be instantiated once, and putting it in the testbench is a good approach.

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 21, 2021, 3:45pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/28 "2021-06-21T15:45:26Z")

</div>

Hi Marius,

Since we have now 1 testbench (includes within it 1 test sequencer process) and eg 2 test harnesses that the testbench instantiates, if I execute within the test sequencer process separate VVC commands of the 2 different eg DUTs, it all works in a sequential fashion ie

eg reseting the ClockCycleCounter followed by reseting the checkStable  
resetting the ClockCycleCounter DUT happens first (ClockCycleCounter belongs to the 1st test harness) and resetting of the CheckStable DUT happens next (checkStable belongs to the 2nd test harness).

So both resets could not happen concurrently in this example and thus in the simulation window I see the checkStable block having undefined reset output value at the start until the ClockCycleCounter reset completes and the CheckStable reset command kickstarts.

The only way I think to run separate concurrent DUT/VVC interfaces commands, if we only want to still have 1 testbench, is to have within it multiple test sequencer processes (ie all can then run in parallel - in this example 2 test sequencer processes within 1 testbench that instantiates 2 test harnesses). Is this the case? Please comment here.

Kind regards,  
Kevin

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [June 22, 2021, 8:19am UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/29 "2021-06-22T08:19:18Z")

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Hi,  
I think you are overcomplicating the test by having 1 testbench and multiple test harness. Can you clarify how you intend to test:

- one DUT at a time
- both DUTs at the same time

I guess you have each DUT instantiated in their own test harness?

The VVC commands are distributed from the test sequencer at no time, i.e. you can distribute many VVC commands to various VVCs at the same time, and the commands distributed to each VVC will be executed in the same order as they were written in the test sequencer. When the VVC command(s) have been sent from the sequencer, you will typically wait for the VVC to finish executing the command (await\_comlpetion() - see Common VVC Methods PDF in uvvm\_vvc\_framework/doc) before you send new commands or check the response from the DUT etc.

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 22, 2021, 8:52am UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/30 "2021-06-22T08:52:08Z")

</div>

Hi Marius,

I agree with you wrt your statement of ‘overcompicating the test by having 1 testbench and multiple test harnesses’…

However, this is what my team asked me to do after a review meeting ie use 1 testbench and multiple test harnesses to verify the whole FPGA. So related DUT interfaces will be instantiated within one test harness together with their VVCs. My choice was to use multiple testbenches but this method was not agreed to use.

The Test sequencer I use is a process within the testbench and VVC commands are issued as follows eg

:::  
log(ID\_SEQUENCER, “Pulse the ClockCycleCounter in\_reset for 10 clock periods”, C\_SCOPE)

counter\_reset(CLOCKCYCLECOUNTER\_VVCT, 1, 10, “Reset counter value”);   
await\_completion(CLOCKCYCLECOUNTER\_VVCT, 1, 11\*C\_CLK\_PERIOD, “Await completion”);

counter\_check(1, “1st counter check”, x"0000", out\_counter(0), in\_clock, ErrCnt, TotalPass, TotalCnt, C\_SCOPE);

::

log(ID\_SEQUENCER, “Pulse the checkStable in\_reset for 10 clock periods”, C\_SCOPE);

checkStable\_reset(CHECKSTABLE\_VVCT, 1, 10, “Reset checkStable module”);

await\_completion(CHECKSTABLE\_VVCT, 1, 11\*C\_CLK\_PERIOD, “Await completion”);

log(ID\_SEQUENCER, “Check the checkStable out\_bus value right after reset”, C\_SCOPE);

checkStable\_check(1, “1st checkStable check - Check out\_bus right after reset”, ‘0’, out\_bus, in\_clk, ErrCnt, TotalPass, TotalCnt, C\_SCOPE);

:::

– Other VVC commands follow in a similar way as above  
:::

* * *

So from the above each VVC command is wait to be completed before a new command is send or check the response from the DUT.

So they are executed in the same order as they were written in the test sequencer and not concurrently. Isn’t this the case here?

& if we like then for the separate test harnesses the VVC commands to be concurrent, 2 separate Test Sequential processes must be included within the 1 testbench (executing separately their VVC commands) wrt this example. Do you agree here?

Kind regards,  
Kevin

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [June 23, 2021, 9:12am UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/31 "2021-06-23T09:12:45Z")

</div>

Hi Kevin,  
Yes, the commands are executed in the same order as written in the sequencer.  
You can call both counter\_reset() and check\_stable\_reset() before the await\_completion() if you want the two VVC commands to be executed at the same time. E.g.

```auto
log(ID_SEQUENCER, "Pulsing ClockCycleCounter and checkStable resets for 10 clk periods", C_SCOPE);
counter_reset(CLOCKCYCLECOUNTER_VVCT, 1, 10, “Reset counter value”); 
checkStable_reset(CHECKSTABLE_VVCT, 1, 10, “Reset checkStable module”);

await_completion(CHECKSTABLE_VVCT, 1, 11*C_CLK_PERIOD, “Await completion”);

log(ID_SEQUENCER, “Checking reset values”, C_SCOPE);
counter_check(1, “1st counter check”, x"0000", out_counter(0), in_clock, ErrCnt, TotalPass, TotalCnt, C_SCOPE);
checkStable_check(1, “1st checkStable check - Check out_bus right after reset”, ‘0’, out_bus, in_clk, ErrCnt, TotalPass, TotalCnt, C_SCOPE);

```

Can both DUTs use the same reset, or are there a reason you need two reset VVCs?

Just as a note; for the reset checking I would probably have created a reset\_checker process inside the test harness, that monitors the DUT reset signal and triggers the checker methods every time the reset signal is released, simplifying your sequencer and ensures that the reset values are checked for every testcase. E.g

```auto
p_reset_checker: process
begin
  while true loop
    wait until reset'event and reset='1'; -- active low reset
    checkStable_check(1, “1st checkStable check - Check out_bus right after reset”, ‘0’, out_bus, in_clk, ErrCnt, TotalPass, TotalCnt, C_SCOPE);
    counter_check(1, “1st counter check”, x"0000", out_counter(0), in_clock, ErrCnt, TotalPass, TotalCnt, C_SCOPE);
  end loop;
  wait;
end process;

```

Br,  
Marius

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<div class="post-metadata">

**Author:** ![KevNug](https://avatars.discourse-cdn.com/v4/letter/k/cdc98d/32.png) [@KevNug](https://forum.uvvm.org/u/KevNug)\
**Post date:** [June 23, 2021, 11:14am UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/32 "2021-06-23T11:14:15Z")

</div>

Hi Marius,

Thanks for your reply wrt calling both counter\_reset() and check\_stable\_reset() before the await\_completion(). The 2 VVC commands are now executed at the same time 🙂

Is there a reason why you have suggested creating a reset\_checker process inside the test harness and not within the testbench?

Kind regards,  
Kevin

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [June 23, 2021, 5:14pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212/33 "2021-06-23T17:14:51Z")

</div>

Hi,  
If you have more than one testcase you will reuse the test harness with all testcases (i.e. sequencers). Putting the reset checking in the harness will ensure that reset values are always checked (i.e. you actually don’t need a testcase for reset checking because it is always checked).

Br,  
Marius

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