# Issue on bitvis\_vip\_scoreboard

**URL:** <https://forum.uvvm.org/t/issue-on-bitvis-vip-scoreboard/399>\
**Category:** VVC\
**Created:** [October 13, 2023, 11:34am UTC](https://forum.uvvm.org/t/issue-on-bitvis-vip-scoreboard/399 "2023-10-13T11:34:54Z")\
**Posts on this page:** 3\
**Page:** 1

<div class="post-metadata">

**Author:** ![Jacinto](https://avatars.discourse-cdn.com/v4/letter/j/6bbea6/32.png) [@Jacinto](https://forum.uvvm.org/u/Jacinto)\
**Post date:** [October 13, 2023, 11:34am UTC](https://forum.uvvm.org/t/issue-on-bitvis-vip-scoreboard/399/1 "2023-10-13T11:34:54Z")

</div>

Hi.  
I’m trying to run an AxiLite testsbench on Ubuntu with GHDL, the process goes well until arrives to entity elaboration, i.e. ghdl -e, when the following error appears:

 ![image](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/184b7a40e59a699439a241dd3bdeca7655dbf8ab.png)

I’m sure that my code is correct due to I’ve compiled and run it on Windows with GHDL too and it works perfectly.  
The code is the following:

```auto
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_axilite;
context bitvis_vip_axilite.vvc_context;

entity axilite_supersimple_tb is
end;

architecture bench of axilite_supersimple_tb is

  component axilite_supersimple
  	generic (
  		C_S_AXI_DATA_WIDTH : integer	:= 32;
  		C_S_AXI_ADDR_WIDTH : integer	:= 4
  	);
  	port (
  		S_AXI_ACLK : in std_logic;
  		S_AXI_ARESETN : in std_logic;
  		S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  		S_AXI_AWPROT : in std_logic_vector(2 downto 0);
  		S_AXI_AWVALID : in std_logic;
  		S_AXI_AWREADY : out std_logic;
  		S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  		S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
  		S_AXI_WVALID : in std_logic;
  		S_AXI_WREADY : out std_logic;
  		S_AXI_BRESP : out std_logic_vector(1 downto 0);
  		S_AXI_BVALID : out std_logic;
  		S_AXI_BREADY : in std_logic;
  		S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  		S_AXI_ARPROT : in std_logic_vector(2 downto 0);
  		S_AXI_ARVALID : in std_logic;
  		S_AXI_ARREADY : out std_logic;
  		S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  		S_AXI_RRESP : out std_logic_vector(1 downto 0);
  		S_AXI_RVALID : out std_logic;
  		S_AXI_RREADY : in std_logic
  	);
  end component;

  constant C_S_AXI_DATA_WIDTH : integer	:= 32;
  constant C_S_AXI_ADDR_WIDTH	: integer	:= 4;
  constant C_CLK_PERIOD : time := 10 ns;
  constant C_AXILITE_VVC_IDX : integer := 1;
  signal clock_ena : boolean := true;
  signal S_AXI_ACLK : std_logic;
  signal S_AXI_ARESETN : std_logic := '1';
  signal S_AXI_AWADDR : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  signal S_AXI_AWPROT : std_logic_vector(2 downto 0);
  signal S_AXI_AWVALID : std_logic;
  signal S_AXI_AWREADY : std_logic;
  signal S_AXI_WDATA : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  signal S_AXI_WSTRB : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
  signal S_AXI_WVALID : std_logic;
  signal S_AXI_WREADY : std_logic;
  signal S_AXI_BRESP : std_logic_vector(1 downto 0);
  signal S_AXI_BVALID : std_logic;
  signal S_AXI_BREADY : std_logic;
  signal S_AXI_ARADDR : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  signal S_AXI_ARPROT : std_logic_vector(2 downto 0);
  signal S_AXI_ARVALID : std_logic;
  signal S_AXI_ARREADY : std_logic;
  signal S_AXI_RDATA : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  signal S_AXI_RRESP : std_logic_vector(1 downto 0);
  signal S_AXI_RVALID : std_logic;
  signal S_AXI_RREADY : std_logic ;
  signal axilite_if : t_axilite_if
    (
        write_address_channel(
            awaddr(C_S_AXI_ADDR_WIDTH-1 downto 0)
        ),
        write_data_channel(
            wdata(C_S_AXI_DATA_WIDTH-1 downto 0),
            wstrb(4-1 downto 0)
        ),
        read_address_channel(
            araddr(C_S_AXI_ADDR_WIDTH-1 downto 0)
        ),
        read_data_channel(
            rdata(C_S_AXI_DATA_WIDTH-1 downto 0)
        )
    );

begin
  --MANDATORY VVC INSTANTIATION TO USE AXILITE VVC
  axilite_vvc : entity bitvis_vip_axilite.axilite_vvc
                        generic map(
                                    GC_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
                                    GC_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
                                    GC_INSTANCE_IDX => C_AXILITE_VVC_IDX
                        )
                        port map(
                              clk => S_AXI_ACLK,
                              axilite_vvc_master_if => axilite_if
                        );
  uut: axilite_supersimple generic map ( 
                                 C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
                                 C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH )
                        port map ( 
                                    S_AXI_ACLK => S_AXI_ACLK ,
                                    S_AXI_ARESETN	=> S_AXI_ARESETN,
                                    -- AXI4 Write Address Channel
                                    S_AXI_AWADDR	=> axilite_if.write_address_channel.awaddr,
                                    S_AXI_AWPROT	=> axilite_if.write_address_channel.awprot,
                                    S_AXI_AWVALID	=> axilite_if.write_address_channel.awvalid,
                                    S_AXI_AWREADY	=> axilite_if.write_address_channel.awready,
                                    -- AXI4 Write Data Channel
                                    S_AXI_WDATA => axilite_if.write_data_channel.wdata,
                                    S_AXI_WSTRB => axilite_if.write_data_channel.wstrb,
                                    S_AXI_WVALID	=> axilite_if.write_data_channel.wvalid,
                                    S_AXI_WREADY	=> axilite_if.write_data_channel.wready,
                                    -- AXI4 Write Response Channel
                                    S_AXI_BRESP => axilite_if.write_response_channel.bresp,
                                    S_AXI_BVALID	=> axilite_if.write_response_channel.bvalid,
                                    S_AXI_BREADY	=> axilite_if.write_response_channel.bready,
                                    -- AXI4 Read Address Channel
                                    S_AXI_ARADDR	=> axilite_if.read_address_channel.araddr,
                                    S_AXI_ARPROT	=> axilite_if.write_address_channel.awprot,
                                    S_AXI_ARVALID	=> axilite_if.read_address_channel.arvalid,
                                    S_AXI_ARREADY	=> axilite_if.read_address_channel.arready,
                                    -- AXI4 Read Data Channel
                                    S_AXI_RDATA => axilite_if.read_data_channel.rdata,
                                    S_AXI_RRESP => axilite_if.read_data_channel.rresp,
                                    S_AXI_RVALID	=> axilite_if.read_data_channel.rvalid,
                                    S_AXI_RREADY	=> axilite_if.read_data_channel.rready );
  --FRAMEWORK INSTANTIATION
  i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
  --CLOCK AND RESET SIGNALS
  clock_generator(S_AXI_ACLK, clock_ena, C_CLK_PERIOD, "AXI Lite Clock Signal");
  gen_pulse(S_AXI_ARESETN,'0', 2*C_CLK_PERIOD, "AXI Lite Reset Signal");
  
  p_axiliteVVC: 
  process
    --FILE MANAGING VARIABLES
    variable v_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 
    variable v_expect : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 
    variable v_addr : unsigned(C_S_AXI_ADDR_WIDTH- 1 downto 0);
  begin
    --MANDATORY INITIALIZATION FOR UVVM FRAMEWORK TO BE READY, i.e replaces the line init_axilite_if_signals
    await_uvvm_initialization(VOID);
    shared_axilite_vvc_config(1).bfm_config.clock_period := C_CLK_PERIOD;
    log(ID_LOG_HDR, "AXI LITE VVC BEGINS HERE ");
    --WRITING PROCESS
    log(ID_LOG_HDR,"WRITING PROCESS");
    v_data:=x"A0A1A2A3";
    v_addr:=x"D";
    S_AXI_AWADDR<=std_logic_vector(v_addr);          
    axilite_write(AXILITE_VVCT, C_AXILITE_VVC_IDX, v_addr, v_data, "Written Data");               
    --READING PROCESS
    log(ID_LOG_HDR,"READING PROCESS");
    S_AXI_ARADDR<=std_logic_vector(v_addr);
    axilite_read(AXILITE_VVCT, 1, v_addr, "Read Data From Register",C_SCOPE);
    wait_until_given_time_after_rising_edge(S_AXI_ACLK,15*C_CLK_PERIOD);  
    --CHECKING PROCESS
    log(ID_LOG_HDR,"CHECKING PROCESS");
    axilite_check(AXILITE_VVCT, 1, v_addr, v_data, "Checked Correctly",ERROR,C_SCOPE);
    wait_until_given_time_after_rising_edge(S_AXI_ACLK,15*C_CLK_PERIOD);  
    std.env.stop;
    wait;
  end process;

end;

```

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<div class="post-metadata">

**Author:** ![UVVM\_Team](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/uvvm_team/32/102_2.png) [@UVVM\_Team](https://forum.uvvm.org/u/UVVM_Team)\
**Post date:** [October 18, 2023, 8:36am UTC](https://forum.uvvm.org/t/issue-on-bitvis-vip-scoreboard/399/2 "2023-10-18T08:36:27Z")

</div>

Thanks for your feedback.  
This then seems to be an issues for the GHDL community.  
It would be good if you could send them this case.

---

<div class="post-metadata">

**Author:** ![UVVM\_Team](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/uvvm_team/32/102_2.png) [@UVVM\_Team](https://forum.uvvm.org/u/UVVM_Team)\
**Post date:** [October 18, 2023, 8:36am UTC](https://forum.uvvm.org/t/issue-on-bitvis-vip-scoreboard/399/3 "2023-10-18T08:36:34Z")

</div>

Closed on October 18, 2023, 8:36am UTC