# Imp port vs a tlm fifo in axi scoreboard in uvm
**URL:** https://forum.uvvm.org/t/imp-port-vs-a-tlm-fifo-in-axi-scoreboard-in-uvm/463
**Category:** General questions
**Tags:** uvvm
**Created:** [November 9, 2024, 10:24am UTC](https://forum.uvvm.org/t/imp-port-vs-a-tlm-fifo-in-axi-scoreboard-in-uvm/463 "2024-11-09T10:24:45Z")
**Posts on this page:** 2
**Page:** 1
### Author:  [@kendu](https://forum.uvvm.org/u/kendu)
#### Post date: [November 9, 2024, 10:24am UTC](https://forum.uvvm.org/t/imp-port-vs-a-tlm-fifo-in-axi-scoreboard-in-uvm/463/1 "2024-11-09T10:24:45Z")
I wanted to know if for AXI transactions can I just do with imp port in my Scoreboard which comes with a write method.
Or is there a case where I will definitely need fifo in my Scoreboard for axi transactions.?
The default way (or more popular)of handling the transactions is getting them on an imp port and write method and using it for expected and actual data.
my design has a single axi master and 34 apb slaves. As far as i know no transaction of axi will get lost since all get captured in the write method.
My intention in scoreboard is to just capture the axi wr data and rd data.
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### Author:  [@EspenTa](https://forum.uvvm.org/u/EspenTa)
#### Post date: [January 2, 2025, 4:19pm UTC](https://forum.uvvm.org/t/imp-port-vs-a-tlm-fifo-in-axi-scoreboard-in-uvm/463/2 "2025-01-02T16:19:32Z")
Hi,
I guess Imp port is a SystemVerilog/UVM concept.
I’m not sure if I understand you correctly.
Is your DUT a system of 34 apb slave modules - all controlled from an apb master?
If so:
- Is the master apb port an input into your system - or just an internal bus inside the DUT?
- are the 34 apb slaves pure data receivers in a data communication system or just different types of slave modules - with a mix of control, status and data registers?
– Espen