# How to get two VVC's on a procedure

**URL:** <https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238>\
**Category:** VVC Framework\
**Tags:** question\
**Created:** [November 4, 2021, 12:11pm UTC](https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238 "2021-11-04T12:11:57Z")\
**Posts on this page:** 3\
**Page:** 1

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [November 4, 2021, 12:11pm UTC](https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238/1 "2021-11-04T12:11:57Z")

</div>

Hi,

I want to move UVVM code to a package.

I want to create procedures where two (or more) different VVC’s

I have this working for one VVC

```auto
<start of file my_pkg.vhd>

...

library bitvis_vip_spi;

use bitvis_vip_spi.vvc_metods_pkg.all;

use bitvis_vip_spi.td_vvc_framework_common_methods_pkg.all;

use bitvis_vip_spi.spi_bfm_pkg.all;

use bitvis_vip_spi.vvc_cmd_pkg.all;

use bitvis_vip_spi.td_target_support_pkg.all;

use bitvis_vip_spi.transaction_pkg.all;

...

procedure my_proc(

    signal VVCT : inout td_vvc_target_record;

    constant VVC_IDX: in integer;

    ...

)

...

<end of file my_pkg.vhd>

```

This goes fine.

But now I want to add another GPIO VVC to it.

So I added this library to my package and on my interface of the procedure

```auto
<start of file my_pkg.vhd>

...

library bitvis_vip_spi;

use bitvis_vip_spi.vvc_metods_pkg.all;

use bitvis_vip_spi.td_vvc_framework_common_methods_pkg.all;

use bitvis_vip_spi.spi_bfm_pkg.all;

use bitvis_vip_spi.vvc_cmd_pkg.all;

use bitvis_vip_spi.td_target_support_pkg.all;

use bitvis_vip_spi.transaction_pkg.all;

library bitvis_vip_gpio;

use bitvis_vip_gpio.vvc_metods_pkg.all;

use bitvis_vip_gpio.td_vvc_framework_common_methods_pkg.all;

use bitvis_vip_gpio.gpio_bfm_pkg.all;

use bitvis_vip_gpio.vvc_cmd_pkg.all;

use bitvis_vip_gpio.td_target_support_pkg.all;

use bitvis_vip_gpio.transaction_pkg.all;

...

procedure my_proc(

    signal VVCT_1 : inout td_vvc_target_record;

    constant VVC_IDX_1: in integer;

    signal VVCT_2 : inout td_vvc_target_record;

    constant VVC_IDX_2: in integer;

    ...

)

...

<end of file my_pkg.vhd>

```

But in my simulation I now get the error:

`Identifier "t_vvc_target_record" is not directly visible.`

And then two suggestions are given for the SPI and for the GPIO.

What do I need to do to make this work?

Rgds,

Eric

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [November 8, 2021, 1:44pm UTC](https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238/2 "2021-11-08T13:44:39Z")

</div>

Hi Eric,  
The t\_vvc\_target\_record is defined and compiled into each VVC, so I suspect that your simulator see the GPIO and the SPI t\_vvc\_target\_record definitions and do not know which one to use. Depending on what you are trying to do - can you use overloads, where the signatures include explicit types (bitvis\_vip\_sbi.t\_vvc\_target\_record and bitvis\_vip\_gpio.t\_vvc\_target\_record)?

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![Eric](https://avatars.discourse-cdn.com/v4/letter/e/898d66/32.png) [@Eric](https://forum.uvvm.org/u/Eric)\
**Post date:** [November 26, 2021, 5:53am UTC](https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238/3 "2021-11-26T05:53:07Z")

</div>

Marius,

Just to let you know that your suggestion fixed this issue.  
Thanks!  
It is now like:

```auto
procedure my_proc(

    signal VVCT_1 : inout bitvis_vip_sbi.td_target_support_pkg.t_vvc_target_record;

    constant VVC_IDX_1: in integer;

    signal VVCT_2 : inout bitvis_vip_gpio.td_target_support_pkg.t_vvc_target_record;

    constant VVC_IDX_2: in integer;

    ...

)

```