# " Failed to acquire semaphore when sending command to VVC"

**URL:** <https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302>\
**Category:** General questions\
**Created:** [July 1, 2022, 5:28pm UTC](https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302 "2022-07-01T17:28:01Z")\
**Posts on this page:** 5\
**Page:** 1

<div class="post-metadata">

**Author:** ![hoser519](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/hoser519/32/98_2.png) [@hoser519](https://forum.uvvm.org/u/hoser519)\
**Post date:** [July 1, 2022, 5:28pm UTC](https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302/1 "2022-07-01T17:28:01Z")

</div>

Hello, I am trying to do a simple verification of an SPI module using a SPI VVC and SBI VVC. I don’t have a lot of experience with uvvm but I think I have set it up correctly but any invocation of VVC command, e.g.

```
sbi_write(SBI_VVCT, 1, x"1000", x"40", "Set baud rate to 9600");

```

results in the message: " Failed to acquire semaphore when sending command to VVC".  
I don’t know what this means.

I will note that I am using Modelsim version 10.4 which is older so maybe that’s a reason.

I hope someone can point me in the right direction. thanks.

Here is the log output:

# Time: 0 ps Iteration: 0 Region: /methods\_pkg File: C:/Users/mike/Documents/BTI\_Projects/DSP\_FIR\_IIR\_sandbox/FlatHierarchy/src/uvvm/script/../uvvm\_util/script/../src/methods\_pkg.vhd

# Loading uvvm\_util.bfm\_common\_pkg(body)

# Loading uvvm\_util.generic\_queue\_pkg(body)

# Loading uvvm\_util.rand\_pkg(body)

# Loading uvvm\_util.func\_cov\_pkg(body)

# Loading uvvm\_vvc\_framework.ti\_protected\_types\_pkg(body)

# Loading uvvm\_vvc\_framework.ti\_vvc\_framework\_support\_pkg(body)

# Loading bitvis\_vip\_clock\_generator.vvc\_cmd\_pkg(body)

# Loading bitvis\_vip\_clock\_generator.td\_target\_support\_pkg(body)

# Loading bitvis\_vip\_clock\_generator.vvc\_methods\_pkg(body)

# Loading bitvis\_vip\_clock\_generator.td\_vvc\_framework\_common\_methods\_pkg(body)

# Loading bitvis\_vip\_spi.transaction\_pkg

# Loading bitvis\_vip\_scoreboard.generic\_sb\_support\_pkg(body)

# Loading bitvis\_vip\_spi.spi\_bfm\_pkg(body)

# Loading bitvis\_vip\_spi.vvc\_cmd\_pkg(body)

# Loading bitvis\_vip\_spi.td\_target\_support\_pkg(body)

# Loading bitvis\_vip\_spi.td\_vvc\_framework\_common\_methods\_pkg(body)

# Loading bitvis\_vip\_scoreboard.generic\_sb\_pkg(body)

# Loading bitvis\_vip\_spi.vvc\_methods\_pkg(body)

# Loading bitvis\_vip\_sbi.transaction\_pkg

# Loading bitvis\_vip\_sbi.sbi\_bfm\_pkg(body)

# Loading bitvis\_vip\_sbi.vvc\_cmd\_pkg(body)

# Loading bitvis\_vip\_sbi.td\_target\_support\_pkg(body)

# Loading bitvis\_vip\_sbi.vvc\_methods\_pkg(body)

# Loading bitvis\_vip\_sbi.td\_vvc\_framework\_common\_methods\_pkg(body)

# Loading misc\_function.misc\_function(body)

# Loading bitvis\_vip\_spi.td\_cmd\_queue\_pkg

# Loading bitvis\_vip\_spi.td\_result\_queue\_pkg

# Loading bitvis\_vip\_spi.td\_vvc\_entity\_support\_pkg(body)

# Loading bitvis\_vip\_sbi.td\_cmd\_queue\_pkg

# Loading bitvis\_vip\_sbi.td\_result\_queue\_pkg

# Loading bitvis\_vip\_sbi.td\_vvc\_entity\_support\_pkg(body)

# Loading ieee.std\_logic\_arith(body)

# Loading ieee.std\_logic\_unsigned(body)

# Loading bitvis\_vip\_clock\_generator.td\_cmd\_queue\_pkg

# Loading bitvis\_vip\_clock\_generator.td\_result\_queue\_pkg

# Loading bitvis\_vip\_clock\_generator.td\_vvc\_entity\_support\_pkg(body)

# Loading sim\_lib.testbench\_spi\_module(sim)

# Loading uvvm\_vvc\_framework.ti\_uvvm\_engine(func)

# Loading bitvis\_vip\_spi.spi\_vvc(behave)

# Loading bitvis\_vip\_sbi.sbi\_vvc(behave)

# Loading spi\_module\_lib.spi\_module(behavioral)

# Loading bitvis\_vip\_clock\_generator.clock\_generator\_vvc(behave)

# UVVM: ID\_CONSTRUCTOR 0.0 ns CLOCK\_GENERATOR\_VVC,1 VVC instantiated.

# UVVM: ID\_CONSTRUCTOR\_SUB 0.0 ns CLOCK\_GENERATOR\_VVC,1 Command queue instantiated and will give a warning when reaching 1000 elements in queue.

# UVVM: ID\_CONSTRUCTOR\_SUB 0.0 ns CLOCK\_GENERATOR\_VVC,1 Result queue instantiated and will give a warning when reaching 1000 elements in queue.

# UVVM: ID\_CONSTRUCTOR 0.0 ns SBI\_VVC,1 VVC instantiated.

# UVVM: ID\_CONSTRUCTOR\_SUB 0.0 ns SBI\_VVC,1 Command queue instantiated and will give a warning when reaching 1000 elements in queue.

# UVVM: ID\_CONSTRUCTOR\_SUB 0.0 ns SBI\_VVC,1 Result queue instantiated and will give a warning when reaching 1000 elements in queue.

# UVVM: ID\_CONSTRUCTOR 0.0 ns SPI\_VVC,1 VVC instantiated.

# UVVM: ID\_CONSTRUCTOR\_SUB 0.0 ns SPI\_VVC,1 Command queue instantiated and will give a warning when reaching 1000 elements in queue.

# UVVM: ID\_CONSTRUCTOR\_SUB 0.0 ns SPI\_VVC,1 Result queue instantiated and will give a warning when reaching 1000 elements in queue.

# UVVM: ID\_UVVM\_SEND\_CMD 0.0 ns TB seq.(uvvm) -\>start\_clock(CLOCK\_GENERATOR\_VVC,1): ‘Starting clock’. [1]

# UVVM: ID\_CMD\_INTERPRETER\_WAIT 0.0 ns CLOCK\_GENERATOR\_VVC,1 ..Interpreter: Waiting for command

# UVVM: ID\_CMD\_INTERPRETER\_WAIT 0.0 ns SBI\_VVC,1 ..Interpreter: Waiting for command

# UVVM: ID\_CMD\_INTERPRETER\_WAIT 0.0 ns SPI\_VVC,1 ..Interpreter: Waiting for command

# UVVM: ID\_CTRL 0.0 ns SBI\_VVC\_SB,1 enable() =\> SB enabled. ‘SBI VVC SB Enabled’

# UVVM: ID\_CTRL 0.0 ns SBI\_VVC\_SB,1 config() =\> config applied to SB.

# UVVM: ID\_CTRL 0.0 ns SBI\_VVC\_SB,1 enable\_log\_msg() =\> message id id\_data enabled.

# UVVM: ID\_CTRL 0.0 ns SPI\_VVC\_SB,1 enable() =\> SB enabled. ‘SPI VVC SB Enabled’

# UVVM: ID\_CTRL 0.0 ns SPI\_VVC\_SB,1 config() =\> config applied to SB.

# UVVM: ID\_CTRL 0.0 ns SPI\_VVC\_SB,1 enable\_log\_msg() =\> message id id\_data enabled.

# UVVM: ID\_CMD\_INTERPRETER 0.0 ns CLOCK\_GENERATOR\_VVC,1 start\_clock(CLOCK\_GENERATOR\_VVC,1). Command received [1]

# UVVM: ID\_CMD\_EXECUTOR 0.0 ns CLOCK\_GENERATOR\_VVC,1 start\_clock(CLOCK\_GENERATOR\_VVC,1) - Will be executed [1]

# UVVM:

# UVVM:

# UVVM: ID\_LOG\_HDR 0.0 ns TB seq. Configuring VVCs

# UVVM: ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

# UVVM:

# UVVM:

# UVVM: ID\_LOG\_HDR 0.0 ns TB seq. SPI Module- Testbench

# UVVM: ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

# UVVM: ID\_SEQUENCER 0.0 ns TB seq.

# UVVM:

# UVVM:

# UVVM: ID\_LOG\_HDR 0.0 ns TB seq. do stuff…

# UVVM: ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

# UVVM: ID\_UVVM\_CMD\_ACK 0.0 ns TB seq.(uvvm) ACK received. [1]

# UVVM: ID\_CLOCK\_GEN 0.0 ns CLOCK\_GENERATOR\_VVC,1 Clock ‘clk’ started

# UVVM: ID\_CMD\_EXECUTOR\_WAIT 0.0 ns SBI\_VVC,1 ..Executor: Waiting for command

# UVVM: ID\_CMD\_EXECUTOR\_WAIT 0.0 ns SPI\_VVC,1 ..Executor: Waiting for command

# UVVM: ID\_CMD\_INTERPRETER\_WAIT 0.0 ns CLOCK\_GENERATOR\_VVC,1 ..Interpreter: Waiting for command

# UVVM: ID\_CMD\_EXECUTOR\_WAIT 0.0 ns CLOCK\_GENERATOR\_VVC,1 ..Executor: Waiting for command

# UVVM:

# UVVM: =============================================================================================================================================================================================

# UVVM: \*\*\* TB\_ERROR #1 \*\*\*

# UVVM: 100 ns TB seq.(uvvm)

# UVVM: Failed to acquire semaphore when sending command to VVC

# UVVM:

# UVVM: Simulator has been paused as requested after 1 TB\_ERROR

# UVVM: \*\*\* To find the root cause of this alert, step out the HDL calling stack in your simulator. \*\*\*

# UVVM: \*\*\* For example, step out until you reach the call from the test sequencer. \*\*\*

# UVVM: =============================================================================================================================================================================================

# UVVM:

# UVVM:

# \*\* Note: stop

# Time: 100 ns Iteration: 500 Instance: /testbench\_spi\_module

# Break in Subprogram alert at C:/Users/mike/Documents/BTI\_Projects/DSP\_FIR\_IIR\_sandbox/FlatHierarchy/src/uvvm/script/../uvvm\_util/script/../src/methods\_pkg.vhd line 3702

# Stopped at C:/Users/mike/Documents/BTI\_Projects/DSP\_FIR\_IIR\_sandbox/FlatHierarchy/src/uvvm/script/../uvvm\_util/script/../src/methods\_pkg.vhd line 3702

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [July 4, 2022, 4:55pm UTC](https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302/2 "2022-07-04T16:55:28Z")

</div>

Hi,  
Did you initialize the UVVM environment in your testbench or test-harness? I.e. include this entity

`i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;`

You will also need to stall your testbench sequencer to allow for the UVVM framework to be ready

```auto
await_uvvm_initialization(VOID)

```

See uvvm\_vvc\_framework/doc/UVVM\_VVC\_Framework\_Essential\_Mechanisms.pdf

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![hoser519](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/hoser519/32/98_2.png) [@hoser519](https://forum.uvvm.org/u/hoser519)\
**Post date:** [July 5, 2022, 8:48pm UTC](https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302/3 "2022-07-05T20:48:55Z")

</div>

Hi, thanks but I am doing that in the testbench.

I am suspecting the old simulator Modelsim 10.6 might be a problem here as the testbench is very simple.

I posting the code here in case I did something wrong:

library misc\_function;  
library spi\_module\_lib;  
library uvvm\_util;  
library bitvis\_vip\_spi;  
library bitvis\_vip\_sbi;  
library uvvm\_vvc\_framework;  
library bitvis\_vip\_clock\_generator;

context uvvm\_util.uvvm\_util\_context;  
context bitvis\_vip\_clock\_generator.vvc\_context;  
context bitvis\_vip\_spi.vvc\_context;  
context bitvis\_vip\_sbi.vvc\_context;

use bitvis\_vip\_sbi.sbi\_bfm\_pkg.init\_sbi\_if\_signals;  
use misc\_function.misc\_function.all;  
use uvvm\_vvc\_framework.ti\_vvc\_framework\_support\_pkg.all;

ENTITY testbench\_spi\_module IS  
END testbench\_spi\_module;

ARCHITECTURE sim OF testbench\_spi\_module IS

```
constant clk_period : time := 20 ns;

--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';

signal	spi_data_in_i : STD_LOGIC_VECTOR(7 downto 0);
signal	spi_data_out_i : STD_LOGIC_VECTOR(7 downto 0);
signal	spi_write_req_i : STD_LOGIC;
signal	spi_busy_i : STD_LOGIC;
		
signal	spi_CPOL_i : STD_LOGIC;   
signal spi_CPHA_i : STD_LOGIC;  
signal	spi_MISO_i : STD_LOGIC;
signal SPI_CLK : STD_LOGIC;
signal SPI_MISO : STD_LOGIC;
signal SPI_MOSI : STD_LOGIC;
signal SPI_CS: STD_LOGIC;

signal SPI_BUS : t_spi_if;
signal SBI_BUS : t_sbi_if (addr(7 downto 0), -- Seems you have to define the length for subtypes with variable lengths otherwise it will complain about undefined
   				 wdata(7 downto 0),
    			rdata(7 downto 0))	:= init_sbi_if_signals(8, 8);

-- Configuration of the SPI bus timings
constant SPI_BFM_CONFIG: t_spi_bfm_config := (
	CPOL => '0',
	CPHA => '0',
	spi_bit_time => 10000 ns, -- Make sure we notice if we forget to set bit time.
	ss_n_to_sclk => 20 ns,
	sclk_to_ss_n => 20 ns,
	inter_word_delay => 0 ns,
	match_strictness => MATCH_EXACT,
	id_for_bfm => ID_BFM,
	id_for_bfm_wait => ID_BFM_WAIT,
	id_for_bfm_poll => ID_BFM_POLL
);

```

BEGIN

```
 -- Every UVVM testbench using VVCs must instantiate the UVVM engine module
UVVM_ENGINE : entity uvvm_vvc_framework.ti_uvvm_engine(func);

-- Instantiate instance 1 of SPI VVC
i1_spi_vvc: entity bitvis_vip_spi.spi_vvc
generic map(
	GC_INSTANCE_IDX => 1,
	GC_MASTER_MODE => false
)
port map(
	spi_vvc_if => SPI_BUS
);

SPI_BUS.ss_n <= SPI_CS;
SPI_BUS.sclk <= SPI_clk;
SPI_BUS.mosi <= SPI_MOSI;
SPI_BUS.miso <= SPI_MISO;

-- Instantiate instance one of SBI VVC
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
	GC_INSTANCE_IDX	=> 1,
	GC_ADDR_WIDTH	=> 8,
	GC_DATA_WIDTH	=> 8
)
port map(
	clk => clk,
	sbi_vvc_master_if => SBI_BUS
);
			       
			       

SBI_BUS.cs <= spi_write_req_i ;
SBI_BUS.addr(7 downto 0) <= (others => '0');
SBI_BUS.wena <= '0';
SBI_BUS.rena <= '0';
SBI_BUS.wdata(7 downto 0) <= spi_data_in_i;
SBI_BUS.ready <= '0';
SBI_BUS.rdata(7 downto 0) <=spi_data_out_i;

-- DUT
DUT : entity spi_module_lib.spi_module
generic map (
    	SPI_HALF_CYCLE => 10, -- 25 cycle (50 cycle for SPI period)
    	SPI_CPOL_MODE => '0', -- clock polarity (1 = high)
    	SPI_CPHA_MODE => '0' -- sample on falling edge when CPOL = '1'
	)
port map (

	clk => clk,
	rst => rst,
	data_in => spi_data_in_i,
	data_out => spi_data_out_i,
	spi_write_req => spi_write_req_i,
	spi_busy => spi_busy_i,
	spi_CPOL => spi_CPOL_i,
	spi_CPHA => spi_CPHA_i,
		
	-- connection to spi device
	SPI_CLK => SPI_clk,
	MISO => SPI_MISO,
	MOSI => SPI_MOSI
    
);

```

## – Clock process definitions

```
CLOCK_GEN : entity bitvis_vip_clock_generator.clock_generator_vvc
generic map(
	GC_CLOCK_PERIOD => clk_period,
	GC_CLOCK_HIGH_TIME => clk_period / 2
)
port map(
	clk => clk
); 

start_clock(CLOCK_GENERATOR_VVCT, 1, "Starting clock");

```

– Stimulus process  
stim\_proc: process  
begin

```
-- Every UVVM sequencer should start with this procedure call when using VVCs
await_uvvm_initialization(VOID);	

log(ID_LOG_HDR, "Configuring VVCs");

-- access the t_vvc_config for GC_INSTANCE_IDX of the vvc that contains all configuration data for VVC
-- defined in spi_bfm_pkg.

shared_spi_vvc_config(1).bfm_config.CPOL := '0';
shared_spi_vvc_config(1).bfm_config.CPHA := '0';
shared_spi_vvc_config(1).bfm_config.spi_bit_time := 1 ms;

shared_sbi_vvc_config(1).bfm_config.use_ready_signal := false;
shared_sbi_vvc_config(1).bfm_config.clock_period:= 10 ns;
shared_sbi_vvc_config(1).bfm_config.setup_time := 2.5 ns;
shared_sbi_vvc_config(1).bfm_config.hold_time := 2.5 ns;

log( ID_LOG_HDR , "SPI Module- Testbench" );
log( ID_SEQUENCER, "" );

log( ID_LOG_HDR , "do stuff...");

  -- hold reset state for 100 ns.
rst <= '1';	   
wait for 100 ns;	
rst <= '0';

-- Send command to SPI Master
sbi_write(SBI_VVCT, 1, x"1000", x"40", "Set baud rate to 9600");
spi_slave_receive_only(SPI_VVCT, 1, "Receive from Peripheral 1 and store data in VVC to be retrieved by means of fetch_result()");
await_completion(SPI_VVCT, 1, 1 ms, "Wait for SPI Transaction to complete", C_SCOPE);

wait;

```

end process;

END;

---

<div class="post-metadata">

**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [July 6, 2022, 5:21pm UTC](https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302/4 "2022-07-06T17:21:26Z")

</div>

> [@hoser519](#):
>
> `start_clock(CLOCK_GENERATOR_VVCT, 1, "Starting clock");`

Hi,  
You need to put this VVC command inside the testbench sequencer, somewhere after `await_uvvm_initialization(VOID);`

Br,  
Marius

---

<div class="post-metadata">

**Author:** ![hoser519](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/hoser519/32/98_2.png) [@hoser519](https://forum.uvvm.org/u/hoser519)\
**Post date:** [July 8, 2022, 5:56pm UTC](https://forum.uvvm.org/t/failed-to-acquire-semaphore-when-sending-command-to-vvc/302/5 "2022-07-08T17:56:56Z")

</div>

Thank you for pointing that out. I am completely missed it. That seems to have fixed the problem for this particular error.