# Collisions with Tready in Axi-Stream UVVM

**URL:** <https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398>\
**Category:** Bitvis VIP AXI-Stream\
**Tags:** uvvm\
**Created:** [October 6, 2023, 12:20pm UTC](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398 "2023-10-06T12:20:53Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![jose9ortiz](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/jose9ortiz/32/123_2.png) [@jose9ortiz](https://forum.uvvm.org/u/jose9ortiz)\
**Post date:** [October 6, 2023, 12:20pm UTC](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398/1 "2023-10-06T12:20:53Z")

</div>

Hello!

I have a question about a conexion in Axi-Stream in BFM.  
I can’t get the Tready signal to work in the case of the slave. A data collision always appears in these signal. I know the problem is in the way that I have done the TB with UVVM because the design with a normal TB works. This design it has an axilite protocols too but the question is only about axi-stream.

 ![image](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/4b1cea8aafe2158f6ed6d7199df8a5fc4c5154ab.png)

The code is:

library IEEE;  
use IEEE.std\_logic\_1164.all;  
use IEEE.numeric\_std.all;  
use IEEE.math\_real.all;  
– UVVM UTIL LIBRARIES  
library uvvm\_util;  
context uvvm\_util.uvvm\_util\_context;  
– UVVM VVC FRAMEWORK LIBRARIES  
library uvvm\_vvc\_framework;  
use uvvm\_vvc\_framework.ti\_vvc\_framework\_support\_pkg.all;  
– AXILITE LIBRARIES  
library bitvis\_vip\_axilite;  
context bitvis\_vip\_axilite.vvc\_context;  
– AXISTREAM LIBRARIES  
library bitvis\_vip\_axistream;  
use bitvis\_vip\_axistream.axistream\_bfm\_pkg.all;  
– FILE READING/WRITING LIBRARIES  
library STD;  
use std.env.all;  
use std.textio.all;  
use ieee.std\_logic\_textio.all;  
use std.env.finish;

entity tb\_axivvc is  
end;

architecture bench of tb\_axivvc is  
component DUT is  
generic (  
– AXI Lite  
C\_S\_AXI\_DATA\_WIDTH : integer := 32;  
C\_S\_AXI\_ADDR\_WIDTH : integer := 4;

```
        -- AXI Stream FIFO
        constant GC_DATA_WIDTH : natural := 8;
        constant GC_USER_WIDTH : natural := 1;
        constant GC_FIFO_DEPTH : natural := 256
    );
    port (
        -- AXI Lite
        S_AXI_ACLK : in std_logic;
        S_AXI_ARESETN : in std_logic;

        S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
        S_AXI_AWPROT : in std_logic_vector(2 downto 0);
        S_AXI_AWVALID : in std_logic;
        S_AXI_AWREADY : out std_logic;
        S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
        S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8) - 1 downto 0);
        S_AXI_WVALID : in std_logic;
        S_AXI_WREADY : out std_logic;
        S_AXI_BRESP : out std_logic_vector(1 downto 0);
        S_AXI_BVALID : out std_logic;
        S_AXI_BREADY : in std_logic;
        S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
        S_AXI_ARPROT : in std_logic_vector(2 downto 0);
        S_AXI_ARVALID : in std_logic;
        S_AXI_ARREADY : out std_logic;
        S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
        S_AXI_RRESP : out std_logic_vector(1 downto 0);
        S_AXI_RVALID : out std_logic;
        S_AXI_RREADY : in std_logic;

        -- AXI Stream FIFO
        -- slave stream interface: data in
        S_AXIS_TREADY : out std_logic;
        S_AXIS_TVALID : in std_logic;
        S_AXIS_TDATA : in std_logic_vector(GC_DATA_WIDTH - 1 downto 0);
        S_AXIS_TUSER : in std_logic_vector(GC_USER_WIDTH - 1 downto 0);
        S_AXIS_TKEEP : in std_logic_vector(GC_DATA_WIDTH / 8 - 1 downto 0);
        S_AXIS_TLAST : in std_logic;
        -- master stream interface: data out
        M_AXIS_TREADY : in std_logic;
        M_AXIS_TVALID : out std_logic;
        M_AXIS_TDATA : out std_logic_vector(GC_DATA_WIDTH - 1 downto 0);
        M_AXIS_TUSER : out std_logic_vector(GC_USER_WIDTH - 1 downto 0);
        M_AXIS_TKEEP : out std_logic_vector(GC_DATA_WIDTH / 8 - 1 downto 0);
        M_AXIS_TLAST : out std_logic;

        EMPTY : out std_logic;
        FULL : out std_logic
    );
end component;

-- CLK-UVVM
constant C_CLK_PERIOD : time := 10 ns;
signal clock_ena : boolean := true;

-- AXI LITE
constant C_S_AXI_DATA_WIDTH : integer := 32;
constant C_S_AXI_ADDR_WIDTH : integer := 4;
constant C_AXILITE_VVC_IDX : integer := 1;

signal S_AXI_ACLK : std_logic;
signal S_AXI_ARESETN : std_logic := '1';

signal S_AXI_AWADDR : std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
signal S_AXI_ARADDR : std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
signal axilite_if : t_axilite_if
(
write_address_channel(
awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)
),
write_data_channel(
wdata(C_S_AXI_DATA_WIDTH - 1 downto 0),
wstrb(4 - 1 downto 0)
),
read_address_channel(
araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)
),
read_data_channel(
rdata(C_S_AXI_DATA_WIDTH - 1 downto 0)
)
);

--AXI STREAM
constant c_max_bytes : natural := 100;

constant GC_VVC_IS_MASTER : boolean := true;
constant GC_INSTANCE_IDX : natural := 1;
constant GC_DATA_WIDTH : natural := 8;
constant GC_USER_WIDTH : natural := 1;
constant C_S_AXIS_TDEST_WIDTH : natural := 1;
constant C_S_AXIS_TID_WIDTH : natural := 1;
constant GC_FIFO_DEPTH : natural := 256;

signal empty : std_logic := '1';
signal full : std_logic := '0';

signal axistream_bfm_config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;

signal axistream_if : t_axistream_if
(
tdata (GC_DATA_WIDTH - 1 downto 0),
tkeep ((GC_DATA_WIDTH / 8) - 1 downto 0),
tuser (GC_USER_WIDTH - 1 downto 0),
tstrb ((GC_DATA_WIDTH / 8) - 1 downto 0),
tdest (C_S_AXIS_TDEST_WIDTH - 1 downto 0),
tid (C_S_AXIS_TID_WIDTH - 1 downto 0)
);

signal axistream_if_s : t_axistream_if
(
tdata (GC_DATA_WIDTH - 1 downto 0),
tkeep ((GC_DATA_WIDTH / 8) - 1 downto 0),
tuser (GC_USER_WIDTH - 1 downto 0),
tstrb ((GC_DATA_WIDTH / 8) - 1 downto 0),
tdest (C_S_AXIS_TDEST_WIDTH - 1 downto 0),
tid (C_S_AXIS_TID_WIDTH - 1 downto 0)
);

```

begin

```
axilite_vvc : entity bitvis_vip_axilite.axilite_vvc
    generic map(
        GC_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
        GC_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
        GC_INSTANCE_IDX => C_AXILITE_VVC_IDX
    )
    port map(
        clk => S_AXI_ACLK,
        axilite_vvc_master_if => axilite_if
    );

utt : DUT
generic map(
    --AXI Lite
    C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
    C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
    --AXI Stream
    GC_DATA_WIDTH => GC_DATA_WIDTH,
    GC_USER_WIDTH => GC_USER_WIDTH,
    GC_FIFO_DEPTH => GC_FIFO_DEPTH
)
port map(
    --AXI Lite
    S_AXI_ACLK => S_AXI_ACLK,
    S_AXI_ARESETN => S_AXI_ARESETN,
    -- AXI4 Write Address Channel
    S_AXI_AWADDR => axilite_if.write_address_channel.awaddr,
    S_AXI_AWPROT => axilite_if.write_address_channel.awprot,
    S_AXI_AWVALID => axilite_if.write_address_channel.awvalid,
    S_AXI_AWREADY => axilite_if.write_address_channel.awready,
    -- AXI4 Write Data Channel
    S_AXI_WDATA => axilite_if.write_data_channel.wdata,
    S_AXI_WSTRB => axilite_if.write_data_channel.wstrb,
    S_AXI_WVALID => axilite_if.write_data_channel.wvalid,
    S_AXI_WREADY => axilite_if.write_data_channel.wready,
    -- AXI4 Write Response Channel
    S_AXI_BRESP => axilite_if.write_response_channel.bresp,
    S_AXI_BVALID => axilite_if.write_response_channel.bvalid,
    S_AXI_BREADY => axilite_if.write_response_channel.bready,
    -- AXI4 Read Address Channel
    S_AXI_ARADDR => axilite_if.read_address_channel.araddr,
    S_AXI_ARPROT => axilite_if.read_address_channel.arprot,
    S_AXI_ARVALID => axilite_if.read_address_channel.arvalid,
    S_AXI_ARREADY => axilite_if.read_address_channel.arready,
    -- AXI4 Read Data Channel
    S_AXI_RDATA => axilite_if.read_data_channel.rdata,
    S_AXI_RRESP => axilite_if.read_data_channel.rresp,
    S_AXI_RVALID => axilite_if.read_data_channel.rvalid,
    S_AXI_RREADY => axilite_if.read_data_channel.rready,
    --AXI STREAM
    -- slave stream interface: data in
    S_AXIS_TREADY => axistream_if.tready,
    S_AXIS_TVALID => axistream_if.tvalid,
    S_AXIS_TDATA => axistream_if.tdata,
    S_AXIS_TUSER => axistream_if.tuser,
    S_AXIS_TKEEP => axistream_if.tkeep,
    S_AXIS_TLAST => axistream_if.tlast,
    -- master stream interface: data out
    M_AXIS_TREADY => axistream_if_s.tready,
    M_AXIS_TVALID => axistream_if_s.tvalid,
    M_AXIS_TDATA => axistream_if_s.tdata,
    M_AXIS_TUSER => axistream_if_s.tuser,
    M_AXIS_TKEEP => axistream_if_s.tkeep,
    M_AXIS_TLAST => axistream_if_s.tlast,

    EMPTY => empty,
    FULL => full
);

-- INIT AXI STREAM BFM
axistream_if <= init_axistream_if_signals(false, axistream_if.tdata'length, axistream_if.tuser'length, axistream_if.tid'length, axistream_if.tdest'length);
wait_until_given_time_after_rising_edge(S_AXI_ACLK, C_CLK_PERIOD);
axistream_bfm_config.clock_period <= C_CLK_PERIOD;
axistream_bfm_config.check_packet_length <= true;

--FRAMEWORK INSTANTIATION
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;

--CLOCK AND RESET SIGNALS
clock_generator(S_AXI_ACLK, clock_ena, C_CLK_PERIOD, "AXI Clock Signal");

--P_SEQUENCER
p_sequencer :
process is
    --Read file seqfile
    file t_file : text open read_mode is "seqfile";
    variable t_line : line;
    variable good : boolean := false;

    --OPCODE DESCRIPTION
    variable opcode : string(1 to 5) := (others => ' ');
    variable subopcode : string(1 to 2) := (others => ' ');

    --Aux variable
    variable aux_text : string(1 to 50) := (others => ' ');
    variable aux : integer;
    constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;

    --AXI Lite
    variable v_data : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
    variable v_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);

    --AXI Stream
    file t_axi_file : text;
    variable t_axi_line : line;
    variable open_status : FILE_OPEN_STATUS;

    variable version_file : string(1 to 11) := (others => ' ');
    variable name_file : string(1 to 11) := (others => ' ');
    variable i : integer := 2; -- Jump space
    variable j : integer := 0;

    variable v_data_array : t_byte_array(0 to c_max_bytes - 1);

    -- RECEIVE AXI STREAM SIGNAL
    variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
    variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
    variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
    variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
    variable v_exp_data_array : t_slv_array(0 to c_max_bytes - 1)(GC_DATA_WIDTH - 1 downto 0);
    variable v_exp_data_length : natural;

begin
    --INITIALIZATION FOR UVVM FRAMEWORK TO BE READY
    --await_uvvm_initialization(VOID);
    shared_axilite_vvc_config(1).bfm_config.clock_period := C_CLK_PERIOD;

    log(ID_LOG_HDR, "START SIMUTALION");

    -- OPCODE
    while not endfile(t_file) loop
        readline(t_file, t_line);
        read(t_line, opcode, good);
        if good /= false then
            case opcode is

                    -- Reset X cicles
                when "RESET" =>
                    read(t_line, aux, good);

                    if good /= false then
                        read(t_line, aux_text(1 to t_line'length));

                        if aux /= 0 then
                            gen_pulse(S_AXI_ARESETN, '0', aux * C_CLK_PERIOD, aux_text);
                        else
                            log(ID_LOG_HDR, "ERROR: RESET N COMMENT", C_SCOPE);
                            log("RESET N COMMENT");
                            increment_expected_alerts_and_stop_limit(ERROR, 1, "RESET N COMMENT");
                        end if;
                    else
                        log(ID_LOG_HDR, "ERROR: RESET N COMMENT", C_SCOPE);
                        log("RESET N COMMENT");
                        increment_expected_alerts_and_stop_limit(ERROR, 1, "RESET N COMMENT");
                    end if;

                    -- Wait X cicles
                when "WAIT " =>
                    read(t_line, aux, good);

                    if good /= false then
                        if aux = 0 then
                            wait;
                        else
                            wait_until_given_time_after_rising_edge(S_AXI_ACLK, C_CLK_PERIOD * aux);
                        end if;
                    else
                        log(ID_LOG_HDR, "ERROR: WAIT N", C_SCOPE);
                        log("WAIT N");
                        increment_expected_alerts_and_stop_limit(ERROR, 1, "WAIT N");
                    end if;

                    -- Comments about text
                when "LOGTX" =>
                    read(t_line, aux, good);
                    if good /= false then
                        case aux is
                            when 0 =>
                                read(t_line, aux_text(1 to t_line'length));
                                log(aux_text);
                            when 1 =>
                                read(t_line, aux_text(1 to t_line'length));
                                log(ID_LOG_HDR, aux_text, C_SCOPE);
                            when others =>
                                log(ID_LOG_HDR, "ERROR: LOGTX [0/1] COMMENT", C_SCOPE);
                                log("LOGTX [0/1] COMMENT");
                                increment_expected_alerts_and_stop_limit(ERROR, 1, "LOGTX [0/1] COMMENT");
                        end case;
                    else
                        log(ID_LOG_HDR, "ERROR: LOGTX [0/1] COMMENT", C_SCOPE);
                        log("LOGTX [0/1] COMMENT");
                        increment_expected_alerts_and_stop_limit(ERROR, 1, "LOGTX [0/1] COMMENT");
                    end if;

                    -- Stop program and report alert and check
                when "STOPP" =>
                    report_check_counters(FINAL);
                    report_alert_counters(FINAL);
                    read(t_line, aux_text(1 to t_line'length));
                    log(ID_LOG_HDR, aux_text, C_SCOPE);
                    file_close(t_file);
                    std.env.stop;

                    -- Use AXI Lite
                when "AXIL " =>
                    read(t_line, subopcode, good);
                    if good /= false then
                        case subopcode is
                                -- Write
                            when "W " =>
                                -- WRITING DATA
                                log(ID_LOG_HDR, "WRITING PROCESS");
                                hread(t_line, v_addr, good);
                                if good /= false then
                                    good := false;

                                    S_AXI_AWADDR <= v_addr;

                                    hread(t_line, v_data, good);
                                    if good /= false then
                                        axilite_write(AXILITE_VVCT, C_AXILITE_VVC_IDX, unsigned(v_addr), v_data, "Written Data");
                                    else
                                        log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite Write Data", C_SCOPE);
                                        log("AXIL W ADDR DATA");
                                        increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite Write Data");
                                    end if;
                                    --AWAITING FOR ACK IS NEEDED 
                                    await_completion(AXILITE_VVCT, C_AXILITE_VVC_IDX, 1000 ns);
                                    wait_until_given_time_after_rising_edge(S_AXI_ACLK, 15 * C_CLK_PERIOD);
                                else
                                    log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite Write ADDR", C_SCOPE);
                                    log("AXIL W ADDR DATA");
                                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite Write ADDR");
                                end if;

                                -- Read
                            when "R " =>
                                -- READING DATA
                                log(ID_LOG_HDR, "READING PROCESS");
                                hread(t_line, v_addr, good);
                                if good /= false then
                                    S_AXI_ARADDR <= v_addr;
                                    axilite_read(AXILITE_VVCT, 1, unsigned(v_addr), "Read Data From Register", C_SCOPE);
                                else
                                    log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite Read Addr", C_SCOPE);
                                    log("AXIL R ADDR");
                                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite Read Addr");
                                end if;

                                -- Check
                            when "C " =>
                                -- CHECKING DATA
                                log(ID_LOG_HDR, "CHECKING PROCESS");
                                hread(t_line, v_addr, good);
                                if good /= false then
                                    hread(t_line, v_data, good);
                                    if good /= false then
                                        S_AXI_ARADDR <= v_addr;
                                        axilite_check(AXILITE_VVCT, 1, unsigned(v_addr), v_data, "Checked Correctly", WARNING, C_SCOPE);
                                    else
                                        log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite Check Data", C_SCOPE);
                                        log("AXIL C ADDR DATA");
                                        increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite Check Data");
                                    end if;
                                else
                                    log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite Check Addr", C_SCOPE);
                                    log("AXIL C ADDR DATA");
                                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite Check Addr");
                                end if;

                            when others =>
                                log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite VVC", C_SCOPE);
                                log("AXIL [W/C] ADDR DATA");
                                log("AXIL R ADDR");
                                increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite VVC");
                        end case;
                    else
                        log(ID_LOG_HDR, "ERROR: OPCODE AXI Lite VVC", C_SCOPE);
                        log("AXIL [W/C] ADDR DATA");
                        log("AXIL R ADDR");
                        increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Lite VVC");
                    end if;

                    -- Use AXI Stream BFM
                when "AXIS " =>
                    read(t_line, subopcode, good);
                    if good /= false then
                        case subopcode is
                                -- Write
                            when "W " =>
                                log(ID_LOG_HDR, "WRITING AXI STREAM PROCESS BFM");
                                read(t_line, aux, good);

                                if good /= false then
                                    i := 0;

                                    while i < aux and good /= false loop
                                        good := false;
                                        hread(t_line, v_data_array(i), good);
                                        if good /= false then
                                            i := i + 1;
                                        else
                                            log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream Write BFM", C_SCOPE);
                                            log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                                            log("AXIS R N");
                                            increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream Write BFM");
                                        end if;
                                    end loop;

                                    if good /= false then
                                        axistream_transmit(v_data_array(0 to aux - 1), "Written Data", S_AXI_ACLK, axistream_if, C_SCOPE, shared_msg_id_panel, axistream_bfm_config);
                                        log("Flag EMPTY: " & to_string(EMPTY));
                                        log("Flag FULL: " & to_string(FULL));
                                    end if;
                                else
                                    log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream Write BFM", C_SCOPE);
                                    log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                                    log("AXIS R N");
                                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream Write BFM");
                                end if;

                                -- Read
                            when "R " =>
                                log(ID_LOG_HDR, "READING AXI STREAM PROCESS BFM");
                                read(t_line, aux, good);

                                if good /= false then
                                    axistream_receive(data_array => v_exp_data_array(0 to aux - 1),
                                    data_length => v_exp_data_length,
                                    user_array => v_exp_user_array,
                                    strb_array => v_exp_strb_array,
                                    id_array => v_exp_id_array,
                                    dest_array => v_exp_dest_array,
                                    msg => "Received",
                                    clk => S_AXI_ACLK,
                                    axistream_if => axistream_if_s,
                                    scope => C_TB_SCOPE_DEFAULT,
                                    msg_id_panel => shared_msg_id_panel,
                                    config => axistream_bfm_config
                                    );
                                    log("Flag EMPTY: " & to_string(EMPTY));
                                    log("Flag FULL: " & to_string(FULL));
                                else
                                    log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream Read BFM", C_SCOPE);
                                    log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                                    log("AXIS R N");
                                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream Read BFM");
                                end if;

                                -- Check
                            when "C " =>
                                log(ID_LOG_HDR, "CHECKING AXI STREAM PROCESS BFM");
                                read(t_line, aux, good);

                                if good /= false then
                                    i := 0;

                                    while i < aux and good /= false loop
                                        good := false;
                                        hread(t_line, v_data_array(i), good);
                                        if good /= false then
                                            i := i + 1;
                                        else
                                            log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream Check BFM", C_SCOPE);
                                            log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                                            log("AXIS R N");
                                            increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream Check BFM");
                                        end if;
                                    end loop;

                                    if good /= false then
                                        axistream_expect(v_data_array(0 to aux - 1), "Checked Correctly", S_AXI_ACLK, axistream_if_s, error, C_SCOPE, shared_msg_id_panel, axistream_bfm_config);
                                        log("Flag EMPTY: " & to_string(EMPTY));
                                        log("Flag FULL: " & to_string(FULL));
                                    end if;
                                else
                                    log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream Check BFM", C_SCOPE);
                                    log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                                    log("AXIS R N");
                                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream Check BFM");
                                end if;
                            when others =>
                                log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream BFM", C_SCOPE);
                                log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                                log("AXIS R N");
                                log("AXIS [WF/CF] fileName");
                                increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream BFM");
                        end case;
                    else
                        log(ID_LOG_HDR, "ERROR: OPCODE AXI Stream BFM", C_SCOPE);
                        log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                        log("AXIS R N");
                        log("AXIS [WF/CF] fileName");
                        increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR: OPCODE AXI Stream BFM");
                    end if;

                when others =>

                    log(ID_LOG_HDR, "ERROR OPCODE: " & to_string(opcode), C_SCOPE);
                    log("RESET N COMMENT");
                    log("WAIT N ");
                    log("LOGTX [0/1] COMMENT");
                    log("STOPP COMMENT");
                    log("AXIL [W/C] ADDR DATA");
                    log("AXIL R ADDR");
                    log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
                    log("AXIS R N");
                    log("AXIS [WF/CF] fileName");

                    increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR OPCODE: " & to_string(opcode));
            end case;
        else
            log(ID_LOG_HDR, "ERROR OPCODE: " & to_string(opcode), C_SCOPE);
            log("RESET N COMMENT");
            log("WAIT N ");
            log("LOGTX [0/1] COMMENT");
            log("STOPP COMMENT");
            log("AXIL [W/C] ADDR DATA");
            log("AXIL R ADDR");
            log("AXIS [W/C] N 0BYTE 1BYTE ... NBYTE");
            log("AXIS R N");
            log("AXIS [WF/CF] fileName");

            increment_expected_alerts_and_stop_limit(ERROR, 1, "ERROR OPCODE: " & to_string(opcode));
        end if;

        -- Init variable
        good := false;
        opcode := (others => ' ');
        subopcode := (others => ' ');
        aux_text := (others => ' ');
        aux := 0;

        v_addr := (others => '0');
        v_data := (others => '0');

        v_data_array := (others => (others => '0'));
        v_exp_data_array := (others => (others => '0'));

        i := 2;
        j := 1;

    end loop;

    file_close(t_file);
    wait;
end process;

```

end;

and the seqfile.txt that I used is:

RESET 2  
WAIT 5  
LOGTX 1 AXI STREAM BFM  
AXIS W 5 01 02 03 04 05  
AXIS C 5 01 02 03 04 05  
STOPP FINISH SIMULATION

\*\*To add more information, I also have the same result of another project but using tstrb in the case of axistream, but with the same kind of code, in which I get the same result with tready, there is always a data collision as soon as it is set to ‘1’. At the top are the signals corresponding to the slave and at the bottom are those corresponding to the master. I cannot show the result because I am new user and I can upload only one image.

Thank you so much.

---

<div class="post-metadata">

**Author:** ![Erick](https://avatars.discourse-cdn.com/v4/letter/e/bbce88/32.png) [@Erick](https://forum.uvvm.org/u/Erick)\
**Post date:** [October 9, 2023, 7:02am UTC](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398/2 "2023-10-09T07:02:20Z")

</div>

Hi,

I think the problem might be related to the combinatorial assignment:  
`axistream_if <= init_axistream_if_signals(false, axistream_if.tdata'length, axistream_if.tuser'length, axistream_if.tid'length, axistream_if.tdest'length);`

You should remove this, as it will drive the signals of the interface in parallel to the p\_sequencer process.

---

<div class="post-metadata">

**Author:** ![jose9ortiz](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/jose9ortiz/32/123_2.png) [@jose9ortiz](https://forum.uvvm.org/u/jose9ortiz)\
**Post date:** [October 9, 2023, 9:21am UTC](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398/3 "2023-10-09T09:21:29Z")

</div>

Hello!

Thank you! I fixed the mistake about Tready, but I still have the error about axistream\_expect that appear when I try with Trdy to ask the data from the FIFO. Modelsim tells me that all tkeep bits should be ‘1’. they are ‘Z’.

 ![image](https://europe1.discourse-cdn.com/flex017/uploads/uvvm/original/1X/f0f864fdb3cfe580bd22b46f16934b98405bdf66.png)

Best regards

---

<div class="post-metadata">

**Author:** ![Erick](https://avatars.discourse-cdn.com/v4/letter/e/bbce88/32.png) [@Erick](https://forum.uvvm.org/u/Erick)\
**Post date:** [October 11, 2023, 5:40am UTC](https://forum.uvvm.org/t/collisions-with-tready-in-axi-stream-uvvm/398/4 "2023-10-11T05:40:56Z")

</div>

Are you driving the tkeep signal from the DUT?