# Check\_stable bug? **URL:** \ **Category:** Utility Library\ **Tags:** uvvm\ **Created:** [June 11, 2020, 9:15am UTC](https://forum.uvvm.org/t/check-stable-bug/69 "2020-06-11T09:15:07Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![cartfjord](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/cartfjord/32/39_2.png) [@cartfjord](https://forum.uvvm.org/u/cartfjord)\ **Post date:** [June 11, 2020, 9:15am UTC](https://forum.uvvm.org/t/check-stable-bug/69/1 "2020-06-11T09:15:07Z")
Hi I just got this message from my test bench: “check\_stable() =\> Failed. Switched from 0 to 0 1.848 ns ago. Expected stable for 420000000 ps”. Switched from 0 to 0 shouldn’t count as unstable, or? ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 12, 2020, 6:16am UTC](https://forum.uvvm.org/t/check-stable-bug/69/2 "2020-06-12T06:16:49Z")
Hi, I agree, this does not look right. Can you post more of the code so we can have a look at what is happening? Kind regards, Marius ---
**Author:** ![cartfjord](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/cartfjord/32/39_2.png) [@cartfjord](https://forum.uvvm.org/u/cartfjord)\ **Post date:** [June 12, 2020, 7:32am UTC](https://forum.uvvm.org/t/check-stable-bug/69/3 "2020-06-12T07:32:10Z")
Unfortunately, I cannot due to NDA. But I suspect the following happens: at time t + delta\_0 the signal changes to ‘1’. at time t + delta\_1 the signal changes back to ‘0’. Even though the signal is never changed in reality, the _target’last\_event_ used in _check\_stable()_ is updated by the change in the delta cycle. And _last\_value\_string_ is updated with the value at t + delta\_1 which is ‘0’. ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [June 15, 2020, 10:17am UTC](https://forum.uvvm.org/t/check-stable-bug/69/4 "2020-06-15T10:17:42Z")
Hi, is your signal a std\_logic? Which simulator are you using? I do not see how you are able to get equal values as value and last\_value should always differ: procedure check\_stable( signal target : std\_logic; constant stable\_req : time; constant alert\_level : t\_alert\_level; constant msg : string; constant scope : string := C\_TB\_SCOPE\_DEFAULT; constant msg\_id : t\_msg\_id := ID\_POS\_ACK; constant msg\_id\_panel : t\_msg\_id\_panel := shared\_msg\_id\_panel; constant caller\_name : string := “check\_stable()”; constant value\_type : string := “std\_logic” ) is constant value\_string : string := to\_string(target); constant last\_value\_string : string := to\_string(target’last\_value); constant last\_change : time := target’last\_event; constant last\_change\_string : string := to\_string(last\_change, ns); begin protected\_check\_counters.increment(CHECK\_STABLE); ``` if (last_change >= stable_req) then log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel); else alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " & value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope); end if; ``` end; Br, Marius ---
**Author:** ![cartfjord](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/cartfjord/32/39_2.png) [@cartfjord](https://forum.uvvm.org/u/cartfjord)\ **Post date:** [June 17, 2020, 1:28pm UTC](https://forum.uvvm.org/t/check-stable-bug/69/5 "2020-06-17T13:28:05Z")
Hi, yes it is a std\_logic. The simulator I am currently using is “Riviera-PRO version 2019.04.134.7332 built for Linux64”. Best regards, Christian ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [July 27, 2020, 10:39am UTC](https://forum.uvvm.org/t/check-stable-bug/69/6 "2020-07-27T10:39:36Z")
Hi, I still belive this is a simulator bug, i.e. current value and last value should not be equal. I will try to see if I can recreate the error you are having. Br, Marius ---
**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\ **Post date:** [August 7, 2020, 10:27am UTC](https://forum.uvvm.org/t/check-stable-bug/69/7 "2020-08-07T10:27:04Z")
Hi Christian, I’ve tested a check\_stable() method with a delta pulse in Riviera-Pro version 2019.04.134.7332 built for Windows, with the following test setup and do not experience the same bug as you: ``` library IEEE; use IEEE.std_logic_1164.all; library uvvm_util; context uvvm_util.uvvm_util_context; entity support_tb is generic ( GC_TEST : string := "UVVM" ); end entity; architecture func of support_tb is constant C_CLK_PERIOD : time := 10 ns; constant C_SCOPE : string := "SUPPORT_TB"; signal delta_pulse : std_logic := '0'; begin p_main: process begin set_log_file_name(GC_TEST & "_Log.txt"); set_alert_file_name(GC_TEST & "_Alert.txt"); set_alert_stop_limit(TB_ERROR,1); if GC_TEST = "support_1" then wait for 3*C_CLK_PERIOD; check_stable(delta_pulse, 3*C_CLK_PERIOD, TB_ERROR, "Check pulse signal stable"); else alert(tb_error, "Unsupported test: " & GC_TEST); end if; ----------------------------------------------------------------------------- -- Ending the simulation ----------------------------------------------------------------------------- wait for 1000 ns; -- to allow some time for completion report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail) log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE); -- Finish the simulation std.env.stop; wait; -- to stop completely end process p_main; p_pulser: PROCESS begin wait for C_CLK_PERIOD; gen_pulse(delta_pulse, 0 ns, BLOCKING, "Creating delta pulse"); wait; end process; end func; # KERNEL: UVVM: ID_GEN_PULSE 10.0 ns TB seq. Pulsed to 1 for 0 ps. 'Pulsing a delta_pulse' # KERNEL: UVVM: # KERNEL: UVVM: ========================================================================================================================================================================= # KERNEL: UVVM: ***TB_ERROR #1*** # KERNEL: UVVM: 30 ns TB seq. # KERNEL: UVVM: check_stable() => Failed. Switched from 1 to 0 20 ns ago. Expected stable for 30000 ps # KERNEL: UVVM: Check pulse signal stable # KERNEL: UVVM: # KERNEL: UVVM: Simulator has been paused as requested after 1 TB_ERROR # KERNEL: UVVM: ***To find the root cause of this alert, step out the HDL calling stack in your simulator.*** # KERNEL: UVVM: ***For example, step out until you reach the call from the test sequencer.*** # KERNEL: UVVM: ========================================================================================================================================================================= ``` Br, Marius