# An UVVM case study

**URL:** <https://forum.uvvm.org/t/an-uvvm-case-study/507>\
**Category:** Uncategorized\
**Created:** [December 18, 2025, 8:37pm UTC](https://forum.uvvm.org/t/an-uvvm-case-study/507 "2025-12-18T20:37:27Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Gastone](https://avatars.discourse-cdn.com/v4/letter/g/58f4c7/32.png) [@Gastone](https://forum.uvvm.org/u/Gastone)\
**Post date:** [December 18, 2025, 8:37pm UTC](https://forum.uvvm.org/t/an-uvvm-case-study/507/1 "2025-12-18T20:37:28Z")

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Hi everyone!

In these days I pick-up an old (and finished) university project - the implementation of a CORDIC in vectoring mode and I told me: “Why don’t exercise my experience in UVVM usage to test it?”

> **[GitHub - un-lo-so/CORDIC: A CORDIC implementation in VHDL - verified with...](https://github.com/un-lo-so/CORDIC)**
>
> A CORDIC implementation in VHDL - verified with UVVM

please note:

- This is a WIP
- The report is (for now) in Italian (because it’s the same one that was used to present the project to the teacher).

I hope to provide, at novices of UVVM (like me), a simple example of case study in order to examine it and understand the philosophy of UVVM.

Comments are welcome!